ds1075 ETC-unknow, ds1075 Datasheet - Page 5

• Manufacturer Part Number: ds1075
• Description: Econoscillator/divider
• Manufacturer: ETC-unknow

PDN
This bit is used to determine the function of the PDN/
SELX pin. If PDN=0, the PDN/SELX pin can be used to
determine the timing reference (either the internal oscil-
lator or an external reference/crystal). If PDN=1, the
PDN/SELX pin is used to put the device into power–
down mode.
EN0
This bit is used to determine whether the OUT0 pin is
active or not. If EN0 =1, OUT0 is disabled (High–imped-
ance). If EN0=0, the internal reference clock (MCLK) is
output from OUT0. The OE pin has no effect on OUT0,
but OUT0 is disabled as part of the power–down
sequence.
N
These nine bits determine the value of the program-
mable divider. The range of divisor values is from 2 to
513, and is equal to the programmed value of N plus 2:
Table 3
NOTE:
The maximum value of N is constrained by the minimum
output frequency. If the internal clock is selected,
FIGURE 4
MCLK
OUT
OE
000000000
000000001
111111111
VALUES
BIT
.
.
.
.
.
t
SU
t
M
DIVISOR (N)
t
VALUE
en
513
2
3
.
.
.
.
.
t
d
INTOSC/(M*N) must be greater than f
external clock is selected, EXTCLK/N must be greater
than f
applicable, must exceed f
OPERATION OF OUTPUT ENABLE
Since the output enable, internal master oscillator
and/or external master oscillator are likely all asynchro-
nous there is the possibility of timing difficulties in the
application. To minimize these difficulties the DS1075
features an “enabling sequencer” to produce predict-
able results when the device is enabled and disabled. In
particular the output gating is configured so that trun-
cated output pulses can never be produced.
Enable timing
The output enable function is produced by sampling the
OE input with the output from the prescaler mux (MCLK)
and gating this with the output from the programmable
divider. The exact behavior of the device is therefore
dependent on the setup time (t
the OE input to the rising edge of MCLK. If the actual
setup time is less than t
cycle of MCLK will be required to complete the enable or
disable operation (see diagrams). This is unlikely to be
of any consequence in most applications, and then only
if the value for N is small. In general, the output will make
its first positive transition between approximately one
and two clock periods of MCLK after the rising edge
of OE.
OUTmin
. (If DIV1=1, then INTOSC or EXTCLK, as
t
t
MAX VALUE OF t
MIN VALUE OF t
M
d
= PROP DELAY FROM MCLK
= PERIOD OF MCLK
SUEM
OUTmin
en
en
then one more complete
= t
SU
= t
SUEM
).
SUEM
) from a transition on
+ t
+ 2 t
M
OUTmin
M
+ t
TO OUT
+ t
d
101697 5/16
d
DS1075
; if the