si5325 Silicon Laboratories, si5325 Datasheet
si5325
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si5325 Summary of contents
Page 1
... PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5325 is ideal for providing clock multiplication in high performance . timing applications ...
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... Si5325 Table 1. Performance Specifications (V = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Temperature Range T A Supply Voltage V DD Supply Current I DD Input Clock Frequency CK F (CKIN1, CKIN2) Output Clock Frequency CK OF (CKOUT1, CKOUT2) Input Clocks (CKIN1, CKIN2) Differential Voltage Swing CKN DPP ...
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... MHz offset Phase Noise @ 100 kHz Offset Max spur @ > < 100 MHz) Still Air www.silabs.com/timing Symbol DIG T JCT T STG Preliminary Rev. 0.3 Si5325 Min Typ Max Unit — 0.6 TBD ps rms — 0.6 TBD ps rms — 0.05 0.1 dB — ...
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... Si5325 622 MHz In, 622 MHz Out BW=877 kHz -50 -70 -90 -110 -130 -150 -170 1000 10000 OC-48, 12 kHz to 20 MHz OC-192, 20 kHz to 80 MHz OC-192, 4 MHz to 80 MHz OC-192, 50 kHz to 80 MHz Broadband, 800 MHz 4 100000 1000000 Offset Frequency (Hz) Figure 1. Typical Phase Noise Plot ...
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... CKIN2+ Si5325 CKIN2– 82 Ω 82 Ω Control Mode (H) CMODE Reset RST *Note: Assumes differential LVPECL termination (3 clock inputs. Figure 3. Si5325 Typical Application Circuit (SPI Control Mode) Preliminary Rev. 0.3 1 µF 0.1 µF 0.1 µF 0.1 µF 0.1 µF CKOUT1+ + 100 Ω CKOUT1– – ...
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... GHz. The device provides virtually any frequency translation combination across this operating range. Independent dividers are available for each input clock and output clock, so the Si5325 can accept input clocks at different frequencies and it can generate output clocks at different frequencies. The ...
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... Pin Descriptions: Si5325 Pin numbers are preliminary and subject to change. Pin # Pin Name I/O 1 RST 14, NC — 18, 30 INT_C1B O Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5325 Register Map RST 1 27 SDI NC ...
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... CKIN1 CKIN1– 21 CS_CA I/O Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5325 Register Map. 8 Signal Level LVCMOS CKIN2 Invalid Indicator. This pin functions as a LOS (and optionally FOS) alarm indi- cator for CKIN2 if CK2_BAD_PIN = CKIN2 present. ...
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... CKOUT2+ 36 CMODE I GND PAD GND GND Note: Internal register names are indicated by underlined italics, e.g. INT_PIN. See Si5325 Register Map. Signal Level LVCMOS Serial Clock/Serial Clock. This pin functions as the serial clock input for both SPI and modes. This pin has a weak pulldown. ...
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... Ordering Guide Ordering Part Output Clock Number Frequency Range Si5325A-C-GM 10–945 MHz 970–1134 MHz 1.213–1.417 GHz Si5325B-C-GM 10–808 MHz Si5325C-C-GM 10–346 MHz 10 Package ROHS6, Pb-Free 36-Lead QFN Yes 36-Lead QFN Yes 36-Lead QFN Yes Preliminary Rev ...
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... Package Outline: 36-Pin QFN Figure 4 illustrates the package details for the Si5325. Table 4 lists the values for the dimensions shown in the illustration. Figure 4. 36-Pin Quad Flat No-lead (QFN) Symbol Millimeters Min Nom A 0.80 0.85 A1 0.00 0.02 b 0.18 0.25 D 6.00 BSC D2 3.95 4.10 e 0.50 BSC E 6.00 BSC E2 3.95 4.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. ...
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... Si5325 5. Recommended PCB Layout 12 Figure 5. PCB Land Pattern Diagram Preliminary Rev. 0.3 ...
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... array of 0.80 mm square openings on 1.05 mm pitch should be used for the center ground pad. Notes (Card Assembly No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Preliminary Rev. 0.3 MIN MAX 0.50 BSC. 5.42 REF. 5.42 REF. 4.00 4.20 4.00 4.20 4.53 — 4.53 — — 0.28 0.89 REF. — 6.31 — 6.31 Si5325 13 ...
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... Changed pins 11 and 15 from NC to VDD in “2. Pin Descriptions: Si5325”. Revision 0.26 to Revision 0.3 Changed 1.8 V operating range to ±5%. Updated Table 1 on page 2. Updated Table 2 on page 3. Added page 4. Updated "1. Functional Description" on page 6. Clarified "2. Pin Descriptions: Si5325" on page 7 including pull-up/pull-down. 14 Preliminary Rev. 0.3 ...
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... N : OTES Preliminary Rev. 0.3 Si5325 15 ...
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... Si5325 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: Clockinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...