si3068 Silicon Laboratories, si3068 Datasheet
si3068
Available stocks
Related parts for si3068
si3068 Summary of contents
Page 1
... Fax machines PDAs ePOS terminals Description The Si3068 is an integrated direct access arrangement (DAA) for use with an integrated DAA system-side module. It includes a V.92 quality codec, dc termination, ac termination, and an integrated hybrid, eliminating the need for an analog front end (AFE), isolation transformer, relays, optoisolator, and 4-wire hybrid. It interfaces directly to the integrated system-side module and features Silicon Laboratories’ ...
Page 2
... Rev. 1.0 Si3068 2 ...
Page 3
... Ringer Impedance and Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.12. DTMF Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.13. Pulse Dialing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 4.14. Receive Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.15. On-Hook Line Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 4.16. Caller 4.17. Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.18. Sample Rate Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.19. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.20. Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 4.21. Revision Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7. Package Outline: 8-Pin Exposed Pad SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Rev. 1.0 Si3068 Page 3 ...
Page 4
... DC Ring Current * Ring Detect Voltage Ring Frequency Ringer Equivalence Number *Note: The ring signal is guaranteed to not be detected below the minimum. The ring signal is guaranteed to be detected above the maximum. TIP Si3068 RING Figure 1. Test Circuit for Loop Characteristics 4 Symbol Test Condition T F-Grade ...
Page 5
... THD kHz, –13 dBm CID IN V CID log (rms /rms noise, excluding harmonics log (rms V /rms noise CID Rev. 1.0 Si3068 Min Typ Max Unit 7.2 — 16 kHz — 5 — Hz — 0.98 — V PEAK — 0.98 — V PEAK — ...
Page 6
... Si3068 Table 4. Digital FIR Filter Characteristics—Transmit and Receive (Sample Rate = 8 kHz °C) A Parameter Passband (0.1 dB) Passband (3 dB) Passband Ripple Peak-to-Peak Stopband Stopband Attenuation Group Delay Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures and 5. 6 Symbol ...
Page 7
... For Figures 2–5, all filter plots apply to a sample rate kHz. The filters scale with the sample rate as follows 0.4125 Fs (0.1 dB 0.45 Fs (–3 dB) where Fs is the sample frequency. Input Frequency—Hz Figure 4. FIR Transmit Filter Response Input Frequency—Hz Figure 5. FIR Transmit Filter Passband Ripple Rev. 1.0 Si3068 7 ...
Page 8
... Si3068 2. Typical Application Schematic 8 Rev. 1.0 ...
Page 9
... MΩ, 1/ kΩ, 1/ Ω, 1/ DNP 0 Ω, 1/ 1.5 MΩ, 1/ 180 kΩ, 1/ MΩ, 1/ Si3068 Zener Diode 1/2 W Rev. 1.0 Si3068 Supplier(s) Panasonic, Murata, Vishay Venkel, SMEC Panasonic Venkel, SMEC Panasonic, Murata, Vishay Venkel, SMEC Venkel, SMEC Central Semiconductor ...
Page 10
... The isolated communications link is disabled by default. To enable it, the PDL bit (Register 6, bit 4) must be cleared. No communication between the system-side and Si3068 can occur until this bit is cleared and the FDT bit (Register 12, bit 6) is high. 10 4.3. Parallel Handset Detection The Si3068 can detect a parallel handset going off- hook ...
Page 11
... Loop Current Sensing The Si3068 measures loop current when off-hook. The LCS[4:0] bits measure loop current with 3.3 mA/bit resolution. The following functions can be performed with the LCS bits: While off-hook, detect if a parallel phone goes on- or off-hook. Determine if sufficient loop current is available for proper operation ...
Page 12
... Si3068 4.5. Line Voltage Sensing The Si3068 measures line voltage when on-hook. The LVS[6:0] bits (register 29) report line voltage with 1 V/bit resolution (typical). The LVS bits can be used to determine if a line is present and idle or in use. Since these operations can be performed while on-hook, there is no need to enter the off-hook state and possibly disturb a call in progress to determine the status of the line ...
Page 13
... FIR filter) should be included in the calculation. 4.7. DC Termination The Si3068 dc I/V characteristics, shown in Figure 8, support a transmit full scale level of –1 dBm at TIP and RING. This requirements of many other countries. ...
Page 14
... Si3068 4.8. Transhybrid Balance The Si3068 contains an on-chip analog hybrid that performs the 2- to 4-wire conversion and near-end echo cancellation. 4.9. Ring Detection Ring detection can be performed by monitoring the ring detector output or by observing the audio CODEC data. The ring detector output can be monitored with the register bits, RDTN, RDTP, and RDT (Register 5, bits 6, 5, and 2) ...
Page 15
... Ringer Impedance and Threshold The ring detector in many DAAs is ac-coupled to the line with a large 1 µF, 250 V decoupling capacitor. The ring detector on the Si3068 is resistively coupled to the line. The network presents a high ringer impedance to the line of approximately 5 MΩ to meet the majority of ...
Page 16
... The power management modes are controlled by the PDL and PDN bits (Register 6, bits [4:3]). Upon powerup or following a reset, the Si3068 is in reset operation. The PDL bit is set, and the PDN bit is cleared. The system-side module is fully operational 16 except for the isolated capacitor link ...
Page 17
... PWMM[1:0] WDTE RDTM FDTM RDTI FDTI RDTN RDTP PDL LSID[3:0] FDT REVB[3:0] TXM ATX[2:0] ADCC ARM[7:0] ATM[7:0] RDLY[1:0] RTO[3:0] RNGV Rev. 1.0 Si3068 Bit 3 Bit 2 Bit 1 Bit 0 PWME IDL AL RDM HBE RXE DODM LCSM DODI LCSI ONHM RDT OH PDN SRC[3:0] DDL REVA[3:0] ...
Page 18
... Si3068 DAA Register 1. Control 1 Bit D7 D6 Name SR Type R/W Reset settings = 0000_0x0x Bit Name 7 SR Software Reset Enables DAA for normal operation Sets all registers to their reset value. Note: Bit clears automatically after being set. 6 Reserved Always write as zero. Reads undefined. 5:4 PWMM[1:0] Pulse-Width Modulation Mode ...
Page 19
... Ring Detect Mode Ring detect on positive threshold Ring detect on positive and negative threshold. 1 HBE Hybrid Enable Disconnects hybrid in transmit path Connects hybrid in transmit path. 0 RXE Receive Enable Receive path disabled Enables receive path WDTE AL R/W R/W Function Rev. 1.0 Si3068 RDM HBE RXE R/W R/W R/W 19 ...
Page 20
... Si3068 DAA Register 3. Interrupt Mask Bit D7 D6 Name RDTM Type R/W Reset settings = 0x0x_00xx Bit Name 7 RDTM Ring Detect Interrupt Mask ring signal does not cause an interrupt ring signal causes an interrupt. 6 Reserved Always write this bit to zero. Reads undefined. 5 FDTM Frame Detect Interrupt Mask ...
Page 21
... The LCS bits have not reached max (all ones The LCS bits have reached max value. If the LCSM bit is set, a hardware interrupt occurs. This bit must be written clear it. 1:0 Reserved Always write this bit to zero. Reads undefined FDTI DODI R/W R/W Function Rev. 1.0 Si3068 LCSI R/W 21 ...
Page 22
... Si3068 DAA Register 5. DAA Control 1 Bit D7 D6 Name RDTN Type R Reset settings = x00x_00x0 Bit Name 7 Reserved Always write this bit to zero. Reads undefined. 6 RDTN Ring Detect Signal Negative ring signal is occurring negative ring signal is occurring. 5 RDTP Ring Detect Signal Positive. ...
Page 23
... Always write this bit to zero. Reads undefined. 4 PDL Powerdown Line-Side Chip Normal operation. Program the clock generator before clearing this bit Powers down the Si3068. 3 PDN Powerdown DAA Normal operation Powers down the DAA logic. A DAA soft reset is required to restore normal operation. ...
Page 24
... Si3068 DAA Register 7. Sample Rate Control Bit D7 D6 Name Type Reset settings = xxxx_0001 Bit Name 7:4 Reserved Always write this bit to zero. Reads undefined. 3:0 SRC[3:0] Sample Rate Control. Sets the sampling rate. 0000 = 7200 Hz 0001 = 8000 Hz 0010 = 8229 Hz 0011 = 8400 Hz 0100 = 9000 Hz ...
Page 25
... Loopback transmit to receive before the filters. Output data is identical to input data. DAA Register 11. System-Side Revision Bit D7 D6 Name LSID[3:0] Type Reset settings = xxxx_xxxx Bit Name Line-Side ID. 7:4 LSID[3:0] 1011 = Si3068 System-Side Revision. 3:0 REVA[3:0] Four bit value indicating the revision of the system-side device Function Function D5 ...
Page 26
... Name Type Reset settings = xxxx_xxxx Bit Name 7:6 Reserved Always write this bit to zero. Reads undefined. 5:2 REVB[3:0] Line-Side Revision. Four-bit value indicating the revision of the Si3068 device. 1000 = Revision A; 1001 = Revision B 1:0 Reserved Always write this bit to zero. Reads undefined Function D5 ...
Page 27
... Receive Mute. 3 RXM 0 = Receive signal is not muted Mutes the receive signal. Analog Receive Gain. 2:0 ARX[2:0] 000 = 0 dB gain 001 = 3 dB gain 010 = 6 dB gain 011 = 9 dB gain 1xx = 12 dB gain Function ATX[2:0] RXM R/W R/W Function Rev. 1.0 Si3068 ARX[2:0] R/W 27 ...
Page 28
... Si3068 DAA Register 16. Reserved Bit D7 D6 Name Type Reset settings = xxx1_xxxx Bit Name 7:0 Reserved Always write this bit to zero. Reads undefined. DAA Register 17. Calibration Bit D7 D6 Name Type Reset Settings = xx0x_xxxx Bit Name 7:6 Reserved Always write this bit to zero. Reads undefined. ...
Page 29
... Reserved Always write this bit to zero. Reads undefined. 1 DOD Dropout Detect Normal operation Dropout detected. 0 Reserved Always write this bit to zero. Reads undefined Function RFWE RDT bit 0 Half-Wave 1 Full-Wave 0 Validated Ring Envelope 1 Ring Threshold Crossing One-Shot Function Rev. 1.0 Si3068 RFWE R DOD R 29 ...
Page 30
... Si3068 DAA Register 20. Call Progress Receive Attenuation Bit D7 D6 Name Type Reset settings = xxxx_0000 Bit Name AOUT Receive Path Attenuation. 7:0 ARM[7:0] When decremented from the default setting, these bits linearly attenuate the AOUT receive path signal used for call progress monitoring. Setting the bits to 0s mutes the AOUT receive path ...
Page 31
... To compensate for error margin and ensure a sufficient ring detection window recom- mended that the calculated value of RMX[5:0] be incremented RMX[5:0] R/W Function RDLY[1:0] Delay 256 ms 10 512 ms 11 1792 -------------------------------------------- - , RMX RAS RMX 5:0 = RAS 5:0 – × 2 f_max Rev. 1.0 Si3068 ≤ × ...
Page 32
... Si3068 DAA Register 23. Ring Validation Control 2 Bit D7 D6 Name RDLY[2] Type R/W Reset settings = 0010_1101 Bit Name 7 RDLY[2] Ring Delay Bit 2. This bit, in combination with the RDLY[1:0] bits, sets the amount of time between when a ring signal is validated and when a valid ring signal is indicated. ...
Page 33
... DAA Register 25-28. Reserved Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 Reserved Always write this bit to zero. Reads undefined RAS[5:0] R/W Function ≥ RAS 5:0 ------------------------------------------ - , RMX RAS × × 2 f_min Function Rev. 1.0 Si3068 ≤ ...
Page 34
... Always write this bit to zero. Reads undefined. DAA Register 60. Line-Side ID Bit D7 D6 Name Type Reset settings = xxxx_x1xx Bit Name 7:3 Reserved Always write this bit to zero. Reads undefined. 2 LSID4 Line-Side ID. LSID = 1 for Si3068 1:0 Reserved Always write this bit to zero. Reads undefined LVS[6:0] R Function Function D5 ...
Page 35
... Provides dc termination to the telephone network Receive Input. Serves as the receive side input from the telephone network. 9 IGND Isolated Ground (exposed pad). Connects to ground on the line-side interface. C1B C2B DCT 2 7 IGND VREG CID Description Rev. 1.0 Si3068 35 ...
Page 36
... Si3068 7. Ordering Guide Part Number* Si3068-B-FS *Note: Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. 36 Package Lead-Free e-Pad SOIC Yes Rev. 1.0 Temp Range °C ...
Page 37
... Package Outline: 8-Pin Exposed Pad SOIC Figure 10 illustrates the package details for the Si3068. Table 10 lists the values for the dimensions shown in the illustration. Figure 10. 8-pin Exposed Pad Small Outline Integrated Circuit (SOIC) Package α Rev. 1.0 Si3068 37 ...
Page 38
... Si3068 Table 10. Package Diagram Dimensions Dimension ∝ Notes: 1. All dimensions shown are in millimeters (mm). 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Recommended card reflow profile is per the JEDEC/IPC J-STD- 020C specification for Small Body Components. ...
Page 39
... N : OTES Rev. 1.0 Si3068 39 ...
Page 40
... Si3068 C I ONTACT NFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: SiDAAinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...