sc9645 Silan, sc9645 Datasheet - Page 8

• Manufacturer Part Number: sc9645
• Description: Cd Digital Servo Signal Processor Slave Mode
• Manufacturer: Silan

3. DAC INTERFACE INPUT FORMAT
CPU INTERFACE TIMING
DATA bus can be used by system CPU and SC9645.
HANGZHOU SILAN MICROELECTRONICS CO.,LTD
Http: www.silan.com.cn
WR, RD are output from system CPU and ACK is output from SC9645 ,the default signal level is high and
1)
2)
System CPU writes: in condition ACK is high.
System CPU read: in condition ACK is high.
a.
b.
c.
d.
e.
a.
b.
c.
d.
e.
CPU sets WR low level at T1 to start writing.
SC9645 sets acknowledge signal: ACK low level at T2.
DATA bus is ready when WR is set from low to high at T3.
SC9645 has finished reading data bus when signal ACK is set from low to high.
One byte write is finished.
CPU sets Rd from high to low at T1 to start reading.
ACK is set from high to low at T2 when SC9645 is ready.
DATA bus is ready when RD is set from low to high at T3.
ACK is set from low to high at T4 by SC9645.
One byte read is finished.
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SC9645
2008.03.24