si4420 Silicon Laboratories, si4420 Datasheet - Page 24

• Manufacturer Part Number: si4420
• Description: Si4420 Universal Ism Band Fsk Transceiver
• Manufacturer: Silicon Laboratories

RX FIFO BUFFERED DATA READ
In this operating mode, incoming data are clocked into a 16 bit FIFO buffer. The receiver starts to fill up the FIFO when the Valid Data
Indicator (VDI) bit and the synchron pattern recognition circuit indicates potentially real incoming data. This prevents the FIFO from being
filled with noise and overloading the external microcontroller.
Polling Mode:
The nFFS signal selects the buffer directly and its content can be clocked out through pin SDO by SCK. Set the FIFO IT level to 1. In this case,
as long as FFIT indicates received bits in the FIFO, the controller may continue to take the bits away. When FFIT goes low, no more bits need
to be taken. An SPI read command is also available.
Interrupt Controlled Mode:
The user can define the FIFO level (the number of received bits), which will generate the nFFIT when exceeded. The status bits report the
changed FIFO status in this case.
FIFO Read Example with FFIT Polling
During FIFO access f
nSEL
nFFS
SDO
FFIT
SCK
FIFO OUT
SCK
0
cannot be higher than f
FO+1
1
FIFO read out
FO+2
2
FO+3
3
FO+4
ref
4
/4, where f
ref
is the crystal oscillator frequency.
Si4420
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