st25e64 STMicroelectronics, st25e64 Datasheet - Page 3

• Manufacturer Part Number: st25e64
• Description: Serial Extended Addressing Compatible With I2c Bus 64k 8k X 8 Eeprom
• Manufacturer: STMicroelectronics

Table 3. Device Select Code
Note: The MSB b7 is sent first.
Table 4. Operating Modes
When writing data to the memory it responds to the
8 bits received by asserting an acknowledge bit
during the 9th bit time. When data is read by the
bus master, it acknowledges the receipt of the data
bytes in the same way.
Data transfers are terminated with a STOP condi-
tion. In this way, up to 8 ST24/25E64 may be
connected to the same I
vidually, allowing a total addressing field of 512
Kbit.
Power On Reset: V
order to prevent data corruption and inadvertent
write operations during power up, a Power On
Reset (POR) circuit is implemented. Untill the V
voltage has reached the POR threshold value, the
internal reset is active: all operations are disabled
and the device will not respond to any command.
In the same way, when V
operating voltage to below the POR threshold
value, all operations are disabled and the device
will not respond to any command. A stable V
must be applied before applying any logic signal.
SIGNALS DESCRIPTION
Serial Clock (SCL). The SCL input pin is used to
synchronize all data in and out of the memory. A
Bit
Device Select
Current Address Read
Random Address Read
Sequential Read
Byte Write
Page Write
Mode
CC
b7
lock out write protect. In
1
2
C bus and selected indi-
CC
drops down from the
RW bit
’1’
’0’
’1’
’1’
’0’
’0’
b6
Device Code
0
b5
1 to 8192
1
Bytes
CC
CC
32
1
1
1
resistor can be connected from the SCL line to V
to act as a pull up (see Figure 3)
Serial Data (SDA). The SDA pin is bi-directional
and is used to transfer data in or out of the memory.
It is an open drain output that may be wire-OR’ed
with other open drain or open collector signals on
the bus. Aresistor must be connectedfrom the SDA
bus line to V
Chip Enable (E0 - E2). These chip enable inputs
are used to set the 3 least significant bits of the 7
bit device select code. They may be driven dynami-
cally or tied to V
select code. Note that the V
inputs are CMOS, not TTL compatible.
Write Control (WC). The Write Control feature
WC is useful to protect the contents of the memory
from any erroneous erase/write cycle. The Write
Control signal is used to enable (WC at V
disable (WC at V
When pin WC is unconnected, the WC input is
internally read as V
When WC = ’1’, Device Select and Address bytes
are acknowledged; Data bytes are not acknow-
ledged.
Refer to the AN404 Application Note for more de-
tailed information about Write Control feature.
b4
0
START, Device Select, RW = ’1’
START, Device Select, RW = ’0’, Address,
reSTART, Device Select, RW = ’1’
As CURRENT or RANDOM Mode
START, Device Select, RW = ’0’
START, Device Select, RW = ’0’
b3
E2
CC
to act as pull up (see Figure 3).
CC
Chip Enable
IL
Initial Sequence
) the internal write protection.
IL
or V
(see Table 5).
E1
b2
SS
to establish the device
ST24E64, ST25E64
IL
and V
b1
E0
IH
levels for the
RW
RW
b0
IH
) or
3/16
CC