st16c554 Exar Corporation, st16c554 Datasheet
st16c554
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st16c554 Summary of contents
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... JUNE 2006 GENERAL DESCRIPTION The ST16C554/554D (554 quad Universal Asynchronous Receiver and Transmitter (UART) with 16 bytes of transmit and receive FIFOs, selectable receive FIFO trigger levels and data rates 1.5 Mbps. Each UART has a set of registers that provide the user with operating status and control, receiver ...
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... TXA 8 Intel Mode Only IOW# 9 TXB 10 CSB# 11 INTB 12 RTSB# 13 GND 14 DTRB# 15 CTSB# 16 ORDERING INFORMATION P N ART UMBER ST16C554CQ64 ST16C554DCQ64 ST16C554DIQ64 ST16C554DCJ68 ST16C554DIJ68 ST68C554CJ68 ST68C554IJ68 DSRA DSRD# CTSA CTSD# DTRA DTRD# VCC 13 57 GND RTSA RTSD# IRQ ...
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... When 16/68# pin is LOW, this input becomes address line A4 which is used for channel selection in the Motorola bus interface. When 16/68# pin is HIGH, this input is chip select D (active low) to enable chan- nel D in the device. When 16/68# pin is LOW, this input is not used and should be connected VCC. 3 ST16C554/554D ...
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... For the 64 pin packages, this pin is bonded to VCC inter- nally in the ST16C554DCQ64 so the INT outputs operate in the continuous interrupt mode. This pin is bonded to GND internally in the ST16C554CQ64 and therefore requires setting MCR bit-3 for enabling the interrupt output pins. ...
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... Reset# pin (active low). This pin functions similarly, but instead of a HIGH pulse minimum LOW pulse will reset the internal registers and outputs. Motorola bus interface is not available on the 64 pin package. No Connection. These pins are not used in either the Intel or Motorola bus modes. 5 ST16C554/554D ...
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... The configuration registers set is 16550 UART compatible for control, status and data transfer. Additionally, each UART channel has 16 bytes of transmit and receive FIFOs, programmable baud rate generator and data rate up to 1.5 Mbps at 5V. The ST16C554 can operate from 2.97 to 5.5 volts. The 554 is fabricated with an advanced CMOS process. ...
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... UART. No clock (oscillator nor external clock) is required for a data bus transaction. Each bus cycle is asynchronous using CS# A-D, IOR# and IOW# or CS#, R/W#, A4 and A3 inputs. All four UART channels share the same data bus for host operations. A typical data bus interconnection for Intel and Motorola mode is shown ST16C554 T I IGURE YPICAL NTEL ...
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... ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO 2.2 Device Reset The RESET input resets the internal registers and the serial interface outputs in all channels to their default state (see Table 13). An active high pulse of longer than 40 ns duration will be required to activate the reset function in the device ...
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... R IN PERATION FOR ECEIVER FOR FCR (FIFO E IT FCR Bit (DMA Mode Disabled) LOW = FIFO below trigger level HIGH = FIFO above trigger level 9 ST16C554/554D “Section Table 3 and 4 Figure 17 through 22. C A-D HANNELS ) NABLED FCR Bit (DMA Mode Enabled) LOW = FIFO above trigger level ...
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... ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO loading or unloading the FIFO in a block sequence determined by the programmed trigger level. The following table show their behavior. Also see T 5: TXRDY# RXRDY# O ABLE AND FCR -0=0 BIT P INS (FIFO D ) ISABLED RXRDY# LOW = 1 byte HIGH = no data ...
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... Clock (Decimal) Clock (HEX) V ALUE 2304 900 384 180 192 ST16C554/554D 16 X Sampling Rate Clock to Transmitter and Receiver DLM DLL D R ATA ATE P ROGRAM ROGRAM E (%) RROR (HEX) V (HEX) ALUE ...
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... ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO 2.9.2 Transmitter Operation in non-FIFO Mode The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled by IER bit-1 ...
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... D ata FIFO Trigger=8 desired FIFO trigger level. FIFO is Enabled bit-0=1 D ata fills to Asking for stopping data w hen data fills above the flow 14 control trigger level to suspend rem ote transm itter. R eceive D ata 13 ST16C554/554D Receive Data Characters RXFIFO1 R eceive D ata C haracters R XFIFO 1 ...
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... ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO 2.11 Internal Loopback The 554 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 10 shows how the modem port signals are re-configured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending ...
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... TO 5.5V QUAD UART WITH 16-BYTE FIFO Table 1 and Table 2). The complete register set is shown EGISTER EAD 16C550 C R OMPATIBLE EGISTERS Read-only Write-only Read/Write Read/Write Read/Write Read-only Write-only Read/Write Read/Write Read-only Read-only Read/Write 15 ST16C554/554D Table 7 C RITE OMMENTS LCR[ LCR[ LCR[ LCR[ ...
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... ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO T ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit IER RD/ ISR RD FIFOs Enabled FCR WR RX FIFO Trigger LCR RD/WR Divisor Enable MCR RD/ LSR ...
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... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the ST16C554 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ...
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... ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO 4.4 Interrupt Status Register (ISR) The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will give the user the current highest pending interrupt level to be serviced, others are queued serviced next ...
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... FIFO crosses the trigger level. T ABLE FCR B 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO Table 10 10: R FIFO T L ECEIVE RIGGER EVEL -7 FCR ECEIVE RIGGER ST16C554/554D shows the complete selections. S ELECTION L EVEL ...
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... ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO 4.6 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register ...
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... Loopback Mode, this bit is used to write the state of the modem RI# interface signal. 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO T 11: P ABLE ARITY SELECTION -4 LCR ARITY SELECTION parity 0 1 Odd parity 1 1 Even parity 0 1 Force parity to mark, HIGH 1 1 Forced parity to space, LOW 21 ST16C554/554D ...
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... ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO MCR[3]: INT Output Enable Enable or disable INT outputs to become active or in three-state. This function is associated with the INTSEL input, see below table for details. This bit is also used to control the OP2# signal during internal loopback mode. INTSEL pin must be LOW during 68 mode. • ...
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... MSR[3]: Delta CD# Input Flag • Logic change on CD# input (default). • Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO 23 ...
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... ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO MSR[4]: CTS Input Status A HIGH on the CTS# pin will stop UART transmitter as soon as the current character has finished transmission, and a LOW will resume data transmission. Normally MSR bit-4 bit is the compliment of the CTS# input. However in the loopback mode, this bit is equivalent to the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when the modem interface is not used ...
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... Bits 7-0 = 0x01 Bits 7-0 = 0x00 Bits 7-0 = 0x00 Bits 7-0 = 0x60 Bits 3-0 = Logic 0 Bits 7-4 = Logic levels of the inputs inverted Bits 7-0 = 0xFF RESET STATE HIGH LOW HIGH HIGH HIGH LOW ST16C554 = Three-State Condition (INTSEL = LOW) ST16C554 = LOW (INTSEL = HIGH) ST16C554D = LOW HIGH (INTSEL = LOW) 25 ST16C554/554D ...
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... ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (64-LQFP) Thermal Resistance (68-PLCC) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS NLESS OTHERWISE NOTED 2 ...
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... TO 5.5V QUAD UART WITH 16-BYTE FIFO FOR NDUSTRIAL RADE ACKAGE 3.3V ± 10 ST16C554/554D 2.97 5.5V LOAD WHERE L L IMITS IMITS 5V ± 10% U NIT MHz ...
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... ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO AC ELECTRICAL CHARACTERISTICS +70 C (-40 + APPLICABLE S P YMBOL ARAMETER T Delay From IOR# To Reset Interrupt RRI T Delay From Start To Interrupt SI T Delay From Initial INT Reset To Transmit Start INT T Delay From IOW# To Reset Interrupt ...
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... RDV Valid Data 29 ST16C554/554D Valid Address T ...
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... ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO F 14 IGURE ODE NTEL ATA A0-A7 Valid Address T AS CS# IOW# D0- IGURE ODE OTOROLA A0-A7 Valid Address T ADS CS# T RWS R/W# T RDA D0- A-D US RITE IMING FOR HANNELS ...
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... T [N -FIFO M ] IMING ON ODE FOR Stop D0:D7 Bit T T SSR SSR 1 Byte 1 Byte in RHR in RHR T T SSR SSR Active Active Data Data Ready Ready ST16C554/554D A-D Valid Address Valid Data 68Write C A-D HANNELS D0:D7 T SSR 1 Byte in RHR T SSR Active Data Ready T RR RXNFM ...
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... ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO F 18 & I IGURE RANSMIT EADY NTERRUPT TX Start (Unloading) D0:D7 Bit IER[1] ISR is read enabled INT* T WRI T SRT TXRDY IOW# (Loading data into THR) *INT is cleared when the ISR is read or when data is loaded into the THR. ...
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... IMING ODE NABLED D0:D7 D0:D7 D0: SSI T SSR T [FIFO M , DMA M IMING ODE Stop Bit D0:D7 S D0:D7 T D0: ST16C554/554D ] C A-D FOR HANNELS D0:D7 D0: FIFO drops below RX Trigger Level FIFO Empties T T RRI RR RXFIFODMA A-D ODE ISABLED FOR HANNELS Last Data Byte ...
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... ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO F 22 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX S D0:D7 (Unloading) IER[1] ISR is read enabled INT* T WRI TXRDY# IOW# (Loading data into FIFO) *INT is cleared when the ISR is read or when at least 1 byte is written to the TX FIFO. ...
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... INCHES MILLIMETERS MIN MAX MIN 0.055 0.063 1.40 0.002 0.006 0.05 0.053 0.057 1.35 0.007 0.011 0.17 0.004 0.008 0.09 0.465 0.480 11.80 0.390 0.398 9.90 0.020 BSC 0.50 BSC 0.018 0.030 0.45 0° 7° 0° 35 ST16C554/554D α L MAX 1.60 0.15 1.45 0.27 0.20 12.20 10.10 0.75 7° ...
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... ST16C554/554D 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO 68 LEAD PLASTIC LEADED CHIP CARRIER (PLCC Note: The control dimension is the inch column SYMBOL ° INCHES ...
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... Copyright 2006 EXAR Corporation Datasheet June 2006. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO D ESCRIPTION NOTICE 37 ST16C554/554D ...
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... ST16C554 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT SSIGNMENT ................................................................................................................................ 2 ORDERING INFORMATION PIN DESCRIPTIONS ........................................................................................................ 3 1.0 PRODUCT DESCRIPTION....................................................................................................................... 6 2.0 FUNCTIONAL DESCRIPTIONS............................................................................................................... 7 2.1 CPU INTERFACE................................................................................................................................................. ST16C554 IGURE YPICAL NTEL 2.2 DEVICE RESET ................................................................................................................................................... 8 2.3 CHANNEL SELECTION....................................................................................................................................... A ABLE HANNEL ELECT A ABLE HANNEL ELECT IN 2 ...
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... IMING ODE ISABLED FOR T [FIFO M , DMA E ] IMING ODE NABLED FOR T [FIFO M , DMA M D IMING ODE ODE ISABLED T [FIFO M , DMA M E IMING ODE ODE NABLED II ST16C554/554D 2.97 5.5V LOAD WHERE A-D ............................................................ 31 A-D .......................................................... 32 C A-D........................................... 32 HANNELS C A-D............................................ 33 HANNELS ] C A-D .............................. 33 FOR HANNELS ] C A-D ............................... 34 FOR HANNELS I ...