sm5838a Nippon Precision Circuits Inc, (NPC), sm5838a Datasheet
sm5838a
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sm5838a Summary of contents
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... OVERVIEW The SM5838AS is a 5120 × 8-bit synchronous FIFO (first in, first out) high-speed line buffer. Internally, it employs static CMOS circuits which mean that it effectively has limitless data hold times. It can operate at speeds up to 33.3MHz (normal-voltage specification). The SM5838AS can be used to easily realize a 1-line delay in high-speed facsimile machines and digital copiers ...
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... Write enable input (write address pointer) 21 DIN3 I Write data input bit 3 22 DIN2 I Write data input bit 2 23 DIN1 I Write data input bit 1 24 DIN0 I Write data input bit 0 SM5838AS 32 32 SRAM Decoder Read address pointer Function 8 DOUT SEIKO NPC CORPORATION —2 ...
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... Pins CLK, RR and RE. 3. Pins DIN0 to DIN7, RW, WE and OE. 4. Pins DOUT0 to DOUT7. Input/Outputs ° 1MHz Parameter Symbol Input capacitance C I Output capacitance C O SM5838AS Condition Condition min Normal-voltage specification 4.5 Low-voltage specification 3.0 − supply Condition min typ ...
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... Normal-voltage (5V) specification 3.0V 0V 5ns CKW CLK t CKW OES OEH DIN SM5838AS 5V supply Condition min typ 30 – 13 – 7 – 3 – 10 – 0 – 13 – 0 – 13 – 0 – 10 – 0 – – – = 3.0/2.5V (5/3V supply). Transition time is measured between V IH Low-voltage (3V) specifi ...
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... Normal-voltage (5V) specification 2.0V 0. CLK t CKW t t OEH DOUT t OH Load circuit 1 VDD 1.8kΩ DOUT 1.1kΩ SM5838AS 5V supply Condition min – “Load circuit 1” “Load circuit 2” 5 Low-voltage (3V) specification 1.8V 1.0V CKW t OES OEH Hi Load circuit 2 30pF 3V supply typ ...
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... CKW CLK t CKW DOUT (n-1) (n) Note the even if a reset period (t RW tion does take place. SM5838AS ). Note that a write reset cycle (read reset cycle) can occur RH reset cycle 0 cycle reset cycle 0 cycle ...
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... Note that data being read was written at least 20 write cycles previously (FIFO minimum delay). Therefore, if (write address pointer) − (read address pointer 19, then a possibility exists that data from the preceding line is output instead. n cycle t CKW CLK t CKW DOUT (n-1) (n) SM5838AS n+1 cycle disable cycle WEH WES WEH WES t DS (n+1) t ...
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... Manipulate the write or read address pointer using disable incrementing to maintain sync with desired delay length. 1H (5120-word) delay line timing 0 cycle 1 cycle CLK DIN 0 1 5120 cycle DOUT SM5838AS n+1 cycle n+2 cycle t t OEH Hi 5119 5120+0 cycle cycle 2 cycle 2 5118 5119 ...
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... DIN 0 1 DOUT n-word delay line timing 3 0 cycle 1 cycle CLK DIN 0 1 DOUT SM5838AS 1H n-1 n+0 2 cycle cycle cycle 2 n-2 n cycle A 1H n-1 n+0 2 cycle cycle cycle n cycle A 1H n-1 n+0 cycle ...
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... SC Furthermore, interpolated line data, with appropriate signal processing separation, can be read out line-by-line by alternating between 2 SM5838AS devices (1 line/device). In reality, however, double the number of devices are required for luminance signal (Y) and color difference signal (C) systems. And triple the number of devices are required for RGB signal systems. ...
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... CLK WE RW nH-1H DIN 909 nH-2H DOUT SM5838AS 5119 5119 5118 0 2 1819 nH+ 909 909 ...
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... Valid 2 pixcels 909 CLK WE RW nH-1H DIN 909 nH-2H 6 DOUT 908* SM5838AS nH nH+ 909 908 0 nH nH+ 909 nH nH- 908 *Output date 902 to 908 forms the preceding 1H data ...
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... Wipe Function (Screen Switching) Because RE and OE operate independently, a screen wipe function can be realized using 2 SM5838AS devices by switching OE LOW/HIGH in field units. Screen wipe (OE changes in field units) 909 CLK WE RW nH-1H (A)DIN 909 nH'-1H (B)DIN 909 ...
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... Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. SM5838AS SEIKO NPC CORPORATION 15-6, Nihombashi-kabutocho, Chuo-ku, ...