sm5841 Nippon Precision Circuits Inc, (NPC), sm5841 Datasheet
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sm5841
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sm5841 Summary of contents
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... NIPPON PRECISION CIRCUITS INC. OVERVIEW The SM5841H is an 8-times oversampling (interpo- lation) digital filter for digital audio reproduction equipment. It accepts 16 or 18-bit input data, and outputs data in 16 20-bit format, making a wide range of interfaces possible. It also features digital deemphasis for 3 sampling frequencies, a noise shaper to reduce quantization noise off- set output and other circuits ...
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... CKSL 4 19 CKO 18 5 VSS 17 (NC (NC WSL2 9 14 DSF1 13 10 DSF2 12 11 RST SM5841H PACKAGE DIMENSIONS 18-pin DIP (Unit: mm) 18 DIN 17 BCKI 16 LRCI 15 OFST 14 VDD 13 WCKO 12 DOL 11 DOR 10 BCKO 1.27MAX 22-pin SOP (Unit: mm) DIN BCKI LRCI OFST ...
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... NC – DSF1 DSF2 RST BCKO O SM5841H LRCI DIN BCKI System Input data Interface Clock Timing Controller Filter and Attenuation Airthmetic block Deemphasis Controler Input/output Interface word length Output date selector VDD VSS Description Input/output data select pins ...
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... Soldering time Recommended Operating Conditions Parameter Supply voltage range Operating temperature range SM5841H Description Right-channel 8fs data output Left-channel 8fs data output Output word clock 5 V supply No connection No connection Output data DC offset select input. Summing ON when HIGH, and OFF when LOW. ...
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... LOW-level input current 2, 3 Input leakage current 2 Input leakage current 384fs = 18.5 MHz, no output load SYS 2. Pins CKSL, OFST 3. Pins LRCI, DIN, BCKI, DSF1, DSF2, WSL1, WSL2, RST 4. Pins CKO, DOL, DOR, BCKO, WCKO SM5841H = Symbol Condition 5.0 V ...
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... CWL Clock pulse cycle t CI Low voltage 3 Parameter Symbol HIGH-level clock pulsewidth t CWH LOW-level clock pulsewidth t CWL Clock pulse cycle t CI CKI SM5841H = Condition System CKSL min clock HIGH 384fs 23 LOW 256fs 35 HIGH 384fs 23 LOW ...
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... Reset timing (RST 3 Parameter RST LOW-level reset pulsewidth Control inputs (DSF1, DSF2 3 Parameter Rise time Fall time SM5841H = Symbol min t 50 BCWH t 50 BCWL t 100 BCY ...
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... CKI to CKO delay CKI to BCKO delay BCKO to DOL, DOR, WCKO delay RST to DOL, DOR delay CKI (CKSL = L) CKI (CKSL = H) BCKO DOL DOR WCKO SM5841H = Symbol Condition t CKI fall to CKO fall CKO t CKI fall to BCKO rise sbH ...
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... OFF -0.0001 -0.00005 0.00000 0.00005 0.0001 0.000 8fs filter band transition response with deemphasis OFF 0.440 SM5841H Frequency 44.1 kHz kHz 24.1 to 152 kHz 152 to 201 kHz 201 to 328 kHz 2.0 3.0 4.0 5.0 Frequency (fs) 0.125 0.250 Frequency (fs) 0.465 ...
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... The maximum deviation from an ideal filter with 0 dB attenuation and 0 phase characteristics for a 1 kHz input signal. Passband response with deemphasis ON (fs = 44.1 kHz Passband response with deemphasis ON (fs = 32/48 kHz SM5841H 32 kHz 0 to 14.5 0.40 to +0. 100 200 500 1k Frequency (Hz) 48kHz 50 100 200 500 1k Frequency (Hz) Sampling frequency 44 ...
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... The interpolation arithmetic block is comprised of 3 cascaded, 2-times FIR interpolation filters, as shown in figure 1. The input signal is sampled at rate fs, and then 8- times oversampling data is output. Sampling noise in the 0.5465fs to 7.4535fs stopband is removed by the interpolation filter. SM5841H Input fs Deemphasis IIR filter fs Attenuator fs 1st FIR ...
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... CKSL CKI CKO Noise Shaper and I/O Data Length (WSL1, WSL2) The SM5841H has functions that can be used to sup- press the level of requantization noise due to the inherent arithmetic rounding-off that occurs in digi- tal signal processing. 16/18-bit input The input interface accepts 16 and 18-bit input source data. That means that if 16-bit source data is digitally processed, for example in a sound fi ...
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... MSB Lch DIN BCKI LRCI SM5841H The internal arithmetic operation and output circuit timing is independent of the input timing. Accord- ingly, phase differences between LRCI, BCKI and CKI do not affect device operation, and any jitter in the data input clock does not cause jitter in the output clock ...
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... The number of output bits is determined by the output bit length selected. Figure 5. 8fs data output timing (CKSL = LOW) SM5841H 8fs serial data is output on independent DOL and DOR channels, in sync with the falling edge of the internal system clock and BCKO clock. The number of BCKO bit clock pulses per word changes depend- ing on the output bit length selected (16/18/20 bits) ...
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... System Reset and Output Muting (RST) System reset The SM5841H must be reset at power-ON by apply- ing a LOW-level pulse on RST. At system reset, the arithmetic and output timing counters are reset on the next LRCI start edge, as long as the CKI clock has already stabilized. The power-ON reset pulse can be applied by a ...
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... TIMING DIAGRAMS Input Timing Examples (DIN, BCKI, LRCI) (MSB) DIN BCKI LRCI (MSB) DIN BCKI LRCI SM5841H 18bit Lch (LSB) (MSB Figure 7. 18-bit input timing 16bit Lch (LSB Figure 8. 16-bit input timing 18bit Rch (LSB) 16bit Rch (MSB) (LSB) NIPPON PRECISION CIRCUITS— ...
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... Figure 9. 8fs data output timing (CKSL = HIGH) System Clock TB BCKO DOL or DOR WCKO 6TB The number of output bits is determined by the output bit length selected. Figure 10. 8fs data output timing (CKSL = LOW) SM5841H 18TB T = 24TB ...
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... DIN SRDATA 2.1168MHz SRCK BCKI 16.9344MHz OA CKI 44.1kHz LRCI DIN DO 2.1168MHz BCO BCKI 16.9344MHz 17MO CKI 44.1kHz LRCI CHCK DIN DOUT 2.1168MHz BCK BCKI CKSL SM5841H WSL1 CKSL SM5841H WSL1 CKSL SM5841H WSL1 CKSL SM5841H WSL1 NIPPON PRECISION CIRCUITS—18 ...
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... This example is for 16-bit input mode, so WSL1 is tied HIGH. For 18-bit mode, WSL1 is tied LOW. 16-bit, 1-DAC (8fs L+R output mode) WCKO DOL SM5841H (16bit Input) DOR BCKO WSL1 WSL2 SM5841H CLOCK BURR - BROWN L. E. PCM58P DATA CLOCK BURR - BROWN L. E. PCM58P ...
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... Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. SM5841H NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan ...