es6178 Jess Technology Group, es6178 Datasheet - Page 4

• Manufacturer Part Number: es6178
• Description: Vibratto-s Dvd Processor Product Brief
• Manufacturer: Jess Technology Group

Table 1
4
Name
TSD1
SEL_PLL1
TSD2
TSD3
MCLK
TBCK
SEL_PLL3
SPDIF_OUT
SPDIF_IN
RSD
RWS
RBCK
CAMIN3
PIXIN3
XIN
XOUT
AVEE
AVSS
DMA[11:0]
DCAS#
DOE#
DSCK_EN
DWE#
DRAS#
DMBS0
DMBS1
DB[15:0]
DCS[1:0]#
DQM
DSCK
DCLK
ES6178 Pin Description (Continued)
SAM0527-052705
77-82, 85-90, 93-96
Pin Numbers
53-58, 61-66
97,100
101
102
105
36
37
38
39
40
41
45
46
47
48
49
70
42
50
51
52
69
71
72
73
74
I/O
I/O
I/O
I/O
O
O
O
O
O
G
O
O
O
O
O
O
O
O
O
O
O
P
I
I
I
I
I
I
I
I
I
I
Definition
Audio transmit serial data output 1.
Refer to the description and matrix for SEL_PLL2 pin 32.
Audio transmit serial data output 2. This pin must be pulled down to VSS via a
4.7-k: resistor for proper operation.
Audio transmit serial data output 3.
Audio master clock for audio DAC.
Audio transmit bit clock. TBCK is an input during reset and subsequently is
programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4).
Clock source select. Strapped to VCC or ground via 4.7-k: resistor; read only
during reset.
S/PDIF output.
S/PDIF input; (5V tolerant input).
Audio receive serial data; (5V tolerant input).
Audio receive frame sync; (5V tolerant input).
Audio receive bit clock; (5V tolerant input).
Camera YUV 3.
CCIR656 input pixel 3.
27-MHz crystal input.
27-MHz crystal output.
Analog power for PLL.
Analog ground for PLL.
DRAM address bus.
DRAM column address strobe.
DRAM output enable.
DRAM clock enable.
DRAM write enable.
DRAM row address strobe.
DRAM bank select 0.
DRAM bank select 1.
DRAM data bus.
DRAM chip select.
Data input/output mask.
Output clock to DRAM.
Clock input to PLL; (5V tolerant input).
SEL_PLL3
0
1
Crystal oscillator
DCLK input
Clock Source
ES6178 PIN DESCRIPTION
ES6178 PRODUCT BRIEF
ESS Technology, Inc.