SST39VF800 Silicon Storage Technology, Inc., SST39VF800 Datasheet - Page 2

• Manufacturer Part Number: SST39VF800
• Description: Megabit 512k 16-bit Multi-purpose Flash
• Manufacturer: Silicon Storage Technology, Inc.

The SST39VF800Q/VF800 also have the Auto Low
Power mode which puts the device in a near standby mode
after data has been accessed with a valid read operation.
This reduces the I
mA to typically 3 µA. The Auto Low Power mode reduces
the typical I
of read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transi-
tion used to initiate another read cycle, with no access time
penalty.
Read
The Read operation of the SST39VF800Q/VF800 is con-
trolled by CE# and OE#, both have to be low for the system
to obtain data from the outputs. CE# is used for device
selection. When CE# is high, the chip is deselected and
only standby power is consumed. OE# is the output control
and is used to gate data from the output pins. The data bus
is in high impedance state when either CE# or OE# is high.
Refer to the Read cycle timing diagram for further details
(Figure 3).
Word Program Operation
The SST39VF800Q/VF800 are programmed on a word-
by-word basis. The Program operation consists of three
steps. The first step is the three-byte load sequence for
Software Data Protection. The second step is to load word
address and word data. During the Word Program opera-
tion, the addresses are latched on the falling edge of either
CE# or WE#, whichever occurs last. The data is latched on
the rising edge of either CE# or WE#, whichever occurs
first. The third step is the internal Program operation which
is initiated after the rising edge of the fourth WE# or CE#,
whichever occurs first. The Program operation, once initi-
ated, will be completed within 20 µs. See Figures 4 and 5
for WE# and CE# controlled Program operation timing
diagrams and Figure 16 for flowcharts. During the Pro-
gram operation, the only valid reads are Data# Polling and
Toggle Bit. During the internal Program operation, the host
is free to perform additional tasks. Any commands issued
during the internal Program operation are ignored.
Sector/Block Erase Operation
The Sector/Block Erase operation allows the system to
erase the device on a sector-by-sector (or block-by-block)
basis. The SST39VF800Q/VF800 offer both small Sector
Erase and Block Erase mode. The sector architecture is
based on uniform sector size of 2 KWord. The Block Erase
mode is based on uniform block size of 32 KWord. The
Sector Erase operation is initiated by executing a six-byte-
command sequence with Sector Erase command (30H)
and sector address (SA) in the last bus cycle. The address
lines A11-A18 are used to determine the sector address.
The Block Erase operation is initiated by executing a six-
© 1999 Silicon Storage Technology, Inc.
DD
active read current to the range of 1 mA/MHz
DD
active read current from typically 15
2
byte command sequence with Block Erase command
(50H) and block address (BA) in the last bus cycle. The
address lines A15-A18 are used to determine the block
address. The sector or block address is latched on the
falling edge of the sixth WE# pulse, while the command
(30H or 50H) is latched on the rising edge of the sixth WE#
pulse. The internal Erase operation begins after the sixth
WE# pulse. The end of Erase operation can be determined
using either Data# Polling or Toggle Bit methods. See
Figures 9 and 10 for timing waveforms. Any commands
issued during the Sector or Block Erase operation are
ignored.
Chip Erase Operation
The SST39VF800Q/VF800 provide a Chip Erase opera-
tion, which allows the user to erase the entire memory array
to the “1” state. This is useful when the entire device must
be quickly erased.
The Chip Erase operation is initiated by executing a six-
byte command sequence with Chip Erase command
(10H) at address 5555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 4 for the command sequence, Figure 8 for timing
diagram, and Figure 19 for the flowchart. Any commands
issued during the Chip Erase operation are ignored.
Write Operation Status Detection
The SST39VF800Q/VF800 provide two software means
to detect the completion of a write (Program or Erase)
cycle, in order to optimize the system write cycle time. The
software detection includes two status bits: Data# Polling
(DQ
mode is enabled after the rising edge of WE#, which
initiates the internal program or erase operation.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to
conflict with either DQ
rejection, if an erroneous result occurs, the software rou-
tine should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the write cycle, otherwise the rejec-
tion is valid.
Data# Polling (DQ
When the SST39VF800Q/VF800 are in the internal Pro-
gram operation, any attempt to read DQ
complement of the true data. Once the Program operation
is completed, DQ
7
) and Toggle Bit (DQ
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
7
7
will produce true data. The device is
)
7
or DQ
6
). The end of write detection
6
. In order to prevent spurious
Advance Information
7
will produce the
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