NJU6635 New Japan Radio Co.,Ltd, NJU6635 Datasheet - Page 17

• Manufacturer Part Number: NJU6635
• Description: 16-character 2-line Dot Matrix Lcd Controller Driver
• Manufacturer: New Japan Radio Co.,Ltd

Write data to CG RAM
Write data to DD RAM
i) Set DD RAM Address
j) Read Busy Flag & Address
k) Write Data to CG or DD RAM
address is written into DB
together with the DD RAM addressing condition. After this instruction, the data writing/reading is
performed into/from the DD RAM.
the busy flag (BF) which indicates the internal operation, is read out from DB
CG RAM or DD RAM is read out from DB
determined by the previous instruction).
(BF)=1. Check the (BF) status before the next write operation.
and code “0” is written into (R/W).
and the binary 8-bit data “DDDDDDDD” are written into the DD RAM. The selection of the CG
RAM or DD RAM is determined by the previous instruction.
automatically according to the entry mode set. And the display shift is also executed according to
the previous entry mode set.
Code
Code
Code
Code
Set DD RAM address instruction is executed when the code “1” is written into DB
The address data mentioned by binary code “AAAAAAA “ is written into the address counter (AC)
The DD RAM address is indicated as follows, which is available for DD RAM address only.
Normal mode condition
Double height size display condition
This instruction reads out the internal status of the NJU6635. When this instruction is executed,
(BF)=1 indicates that internal operation is in progress. The next instruction is inhibited when
Write Data to CG RAM or DD RAM instruction is executed when the code ”1” is written into (RS)
By the execution of this instruction, the binary 5-bit data “DDDDD” are written into the CG RAM,
After this instruction execution, the address increment(+1) or decrement(-1) is performed
DD RAM 1-Line
DD RAM 2-Line (Addressing mode 1)
DD RAM 2-Line (Addressing mode 2)
DD RAM 1-Line
RS
RS
RS
RS
0
0
1
1
R/W
R/W
R/W
R/W
0
1
0
0
DB
DB
DB
DB
BF
D
1
6
7
7
7
7
to DB
Higher order bit
Higher order bit
Higher order bit
Higher order bit
DB
DB
DB
DB
A
A
D
0
6
6
6
6
as shown above.
DB
DB
DB
DB
A
A
D
5
5
5
5
DB
DB
DB
DB
A
A
D
D
6
4
4
4
4
to DB
DB
DB
DB
DB
D
D
A
A
3
3
3
3
0
: (00)
: (10)
: (40)
: (00)
Lower order bit
Lower order bit
Lower order bit
Lower order bit
DD RAM address
DD RAM address
(an address for CG RAM or DD RAM is
DB
DB
DB
DB
A
A
D
D
2
2
2
2
H
H
H
H
– (0F)
– (1F)
– (4F)
– (0F)
DB
DB
DB
DB
A
A
D
D
1
1
1
1
H
H
H
H
DB
DB
DB
DB
D
D
A
A
0
0
0
0
7
NJU6635
=Don’t Care
and the address of
7
and the