sn74ls165n ON Semiconductor, sn74ls165n Datasheet - Page 3

• Manufacturer Part Number: sn74ls165n
• Description: Low Power Schottky
• Manufacturer: ON Semiconductor

FUNCTIONAL DESCRIPTION
flip-flops connected as a shift register, with auxiliary gating
to provide overriding asynchronous parallel entry. Parallel
data enters when the PL signal is LOW. The parallel data can
change while PL is LOW, provided that the recommended
setup and hold times are observed.
inputs perform identically; one can be used as a clock inhibit
10
15
2
1
The SN74LS165 contains eight clocked master/slave RS
For clock operation, PL must be HIGH. The two clock
D
CP
CP
PL
S
1
2
V
GND = PIN 8
CC
= PIN NUMBERS
= PIN 16
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
PL
PL
H
H
H
H
L
PRESET
S
CP
R C
H
1
X
L
11
P
L
CP
Q
Q
0
0
0
X
H
2
L
Q
D
Q
D
Q
PRESET
S
CP
R C
P
0
S
S
0
0
0
12
P
L
Q
Q
1
1
1
Q
P
Q
Q
Q
Q
1
1
0
1
0
1
http://onsemi.com
Q
Q
Q
Q
Q
LOGIC DIAGRAM
P
PRESET
S
CP
R C
2
2
1
2
1
2
TRUTH TABLE
SN74LS165
13
P
L
CONTENTS
Q
Q
2
2
2
Q
P
Q
Q
Q
Q
3
3
2
3
2
3
3
Q
Q
Q
Q
Q
P
PRESET
S
CP
R C
4
by applying a HIGH signal. To avoid double clocking,
however, the inhibit signal should only go HIGH while the
clock is HIGH. Otherwise, the rising inhibit signal will cause
the same response as a rising clock edge. The flip-flops are
edge-triggered for serial operations. The serial input data
can change at any time, provided only that the recommended
setup and hold times are observed, with respect to the rising
edge of the clock.
4
3
4
3
4
14
P
L
Q
Q
Q
P
Q
Q
Q
Q
3
3
3
5
5
4
5
4
5
Q
P
Q
Q
Q
Q
6
6
5
6
5
6
PRESET
S
CP
R C
P
Q
Q
Q
Q
Q
P
3
L
4
Q
Q
7
7
6
7
6
7
4
4
Parallel Entry
RESPONSE
RESPONSE
No Change
No Change
Right Shift
Right Shift
PRESET
S
CP
R C
P
4
L
5
Q
Q
5
5
PRESET
S
CP
R C
P
5
L
Q
6
Q
6
6
PRESET
S
CP
R C
L
P
6
Q
Q
7
7
7
9
7