ad5231 Analog Devices, Inc., ad5231 Datasheet - Page 8

• Manufacturer Part Number: ad5231
• Description: Nonvolatile Memory, 1024-position Digital Potentiometer
• Manufacturer: Analog Devices, Inc.

AD5231
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
O1
CLK
SDI
SDO
GND
V
T
B
W
A
V
WP
PR
CS
RDY
O2
SS
DD
Description
Nonvolatile Digital Output 1. ADDR = 0x1, data bit position D0. For example, to store O1 high, the data bit
format is 0x310001.
Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges.
Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first.
Serial Data Output Pin. Serves readback and daisy-chain functions.
Command 9 and Command 10 activate the SDO output for the readback function, delayed by 24 or 25 clock
pulses, depending on the clock polarity before and after the data-word (see Figure 3, Figure 4, and Table 7).
In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 24 or 25 clock pulses
depending on the clock polarity (see Figure 3 and Figure 4). This previously shifted-out SDI can be used for
daisy-chaining multiple devices.
Whenever SDO is used, a pull-up resistor in the range of 1 kΩ to 10 kΩ is needed.
Ground Pin. Logic ground reference.
Negative Supply. Connect to 0 V for single-supply applications. If V
able to sink 40 mA for 25 ms when storing data to EEMEM.
Reserved for factory testing. Connect to V
Terminal B of RDAC.
Wiper Terminal of RDAC. ADDR (RDAC) = 0x0.
Terminal A of RDAC.
Positive Power Supply Pin.
Optional Write Protect Pin. When active low, WP prevents any changes to the present contents, except PR and
Instruction 1 and Instruction 8 and refreshes the RDAC register from EEMEM. Execute a NOP instruction before
returning to WP high. Tie WP to V
Optional Hardware Override Preset Pin. Refreshes the scratchpad register with current contents of the EEMEM
register. Factory default loads midscale 512
at the logic high transition. Tie PR to V
Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.
Ready. Active-high open-drain output. Identifies completion of Instructions 2, 3, 8, 9, 10, and PR.
Nonvolatile Digital Output 2. ADDR = 0x1, data bit position D1. For example, to store O2 high, the data bit
format is 0x310002.
GND
SDO
CLK
V
SDI
O1
SS
Figure 5. Pin Configuration
DD
B
T
, if not used.
Rev. C | Page 8 of 28
1
2
3
4
5
6
7
8
DD
(Not to Scale)
, if not used.
AD5231
TOP VIEW
DD
10
or V
until EEMEM is loaded with a new value by the user. PR is activated
SS
.
16
15
14
13
12
11
10
9
O2
RDY
CS
PR
WP
V
A
W
DD
SS
is used in dual-supply applications, it must be