ad5171 Analog Devices, Inc., ad5171 Datasheet - Page 18

• Manufacturer Part Number: ad5171
• Description: 64-position Otp Digital Potentiometer
• Manufacturer: Analog Devices, Inc.

AD5171
I
For users who prefer to use external controllers, the AD5171
can be controlled via an I
connected to this bus as a slave device. Referring to Figure 36,
Figure 37, and Figure 38, the 2-wire I
operates as follows:
1.
2.
3.
2
C-COMPATIBLE 2-WIRE SERIAL BUS
The master initiates data transfer by establishing a start
condition, which is when SDA goes from high to low while
SCL is high (Figure 36 and Figure 37). The following byte
is the slave address byte, which consists of the 6 MSBs as a
slave address defined as 010110. The next bit is AD0,
which is an I
of their AD0 bits, two AD5171s can be addressed on the
same bus (Figure 39). The last LSB is the R/ W bit, which
determines whether data is read from, or written to, the
slave device.
The slave address corresponding to the transmitted address
bit responds by pulling the SDA line low during the 9
clock pulse (this is termed the Acknowledge bit). At this
stage, all other devices on the bus remain idle while the
selected device waits for data to be written to, or read from,
its serial register.
The write operation contains one instruction byte more
than the read operation. The instruction byte in the write
mode follows the slave address byte. The MSB of the
instruction byte labeled T is the one-time programming
bit. After acknowledging the instruction byte, the last byte
in the write mode is the data byte. Data is transmitted over
the serial bus in sequences of nine clock pulses (eight data
bits followed by an Acknowledge bit). The transitions on
the SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (Figure 36).
In read mode, the data byte follows immediately after the
acknowledgment of the slave address byte. Data is trans-
mitted over the serial bus in sequences of nine clock pulses
(note the slight difference from the write mode; there are
eight data bits followed by a No Acknowledge bit). Similarly,
the transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL (Figure 38).
2
C device address bit. Depending on the states
2
C-compatible serial bus; the part is
2
C serial bus protocol
th
Rev. B | Page 18 of 24
4.
A repeated write function gives the user flexibility to update the
RDAC output a number of times, except after permanent
programming, addressing, and instructing the part only once.
During the write cycle, each data byte updates the RDAC output.
For example, after the RDAC has acknowledged its slave
address and instruction bytes, the RDAC output updates after
these two bytes. If another byte is written to the RDAC while it
is still addressed to a specific slave device with the same
instruction, this byte updates the output of the selected slave
device. If different instructions are needed, the write mode has to
be started with a new slave address, instruction, and data bytes.
Similarly, a repeated read function of the RDAC is also allowed.
CONTROLLING TWO DEVICES ON ONE BUS
Figure 39 shows two AD5171 devices on the same serial bus.
Each has a different slave address since the state of each AD0
pin is different. This allows each device to be independently
operated. The master device output bus line drivers are open-
drain pull-downs in a fully I
When all data bits have been read or written, a stop
condition is established by the master. A stop condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In the write mode, the master pulls the SDA
line high during the 10
condition (Figure 36 and Figure 37). In the read mode, the
master issues a No Acknowledge for the 9
the SDA line remains high. The master then brings the
SDA line low before the 10
to establish a stop condition (Figure 38).
MASTER
Figure 39. Two AD5171 Devices on One Bus
AD0
AD5171
SDA SCL
th
2
C-compatible interface.
clock pulse to establish a stop
Rp
th
clock pulse, which goes high
5V
Rp
AD0
AD5171
SDA SCL
5V
th
clock pulse, i.e.,
SCL
SDA