ad5933 Analog Devices, Inc., ad5933 Datasheet - Page 16

• Manufacturer Part Number: ad5933
• Description: 1 Msps 12-bit Impedance Converter, Network Analyzer
• Manufacturer: Analog Devices, Inc.

AD5933
1. The master initiates data transfer by establishing a START
condition, defined as a high to low transition on the serial data
line SDA while the serial clock line SCL remains high. This
indicates that a data stream will follow. The slave responds to
the START condition and shift in the next 8 bits, consisting of a
7-bit slave address (MSB first) plus an R/W bit, which
determines the direction of the data transfer, i.e. whether data
will be written to or read from the slave device (0 = write, 1 =
read).
The slave responds by pulling the data line low during the low
period before the ninth clock pulse, known as the acknowledge
bit, and holding it low during the high period of this clock
pulse. All other devices on the bus now remain idle while the
selected device waits for data to be read from or written to it. If
the R/W bit is a 0, then the master will write to the slave device.
If the R/W bit is a 1, the master will read from the slave device.
2. Data is sent over the serial bus in sequences of nine clock
pulses, 8 bits of data followed by an acknowledge bit, which can
be from the master or slave device. Data transitions on the data
line must occur during the low period of the clock signal and
remain stable during the high period, as a low to high transition
when the clock is high may be interpreted as a STOP signal. If
the operation is a write operation, the first data byte after the
slave address is a command byte. This tells the slave device what
to expect next. It may be an instruction telling the slave device
to expect a block write, or it may simply be a register address
that tells the slave where subsequent data is to be written. Since
data can flow in only one direction as defined by the R/W bit, it
is not possible to send a command to a slave device during a
read operation. Before doing a read operation, it may first be
necessary to do a write operation to tell the slave what sort of
read operation to expect and/or the address from which data is
to be read.
3. When all data bytes have been read or written, stop
conditions are established. In WRITE mode, the master will pull
the data line high during the 10th clock pulse to assert a STOP
condition. In READ mode, the master device will release the
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Figure 11.
SDA line during the low period before the 9th clock pulse, but
the slave device will not pull it low. This is known as No
Acknowledge. The master will then take the data line low
during the low period before the 10th clock pulse, then high
during the 10th clock pulse to assert a STOP condition.
WRITING/READING TO THE AD5933
The interface specification defines several different protocols
for different types of read and write operations. The ones used
in the AD5933 are discussed below. The following abbreviations
are used:
S
P
R
W
A
Write Byte/Command Byte
In this operation the master device sends a byte of data to the
slave device. The write byte can either be a data byte write to a
RAM location or can be a command operation.
To write data to a register the command sequence is as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the write
bit (low).
3. The addressed slave device asserts ACK on SDA.
4. The master sends a register address.
5. The slave asserts ACK on SDA.
6. The master sends a data byte.
7. The slave asserts ACK on SDA.
8. The master asserts a STOP condition on SDA to end the
transaction.
-
-
-
-
-
-
Start
Stop
Read
Write
Acknowledge
No Acknowledge
Preliminary Technical Data