ir3500v International Rectifier Corp., ir3500v Datasheet - Page 25

• Manufacturer Part Number: ir3500v
• Description: Xphase3 Vr11.1 Cpu Vtt Control Ic
• Manufacturer: International Rectifier Corp.

The minimum over-current fault latch delay time
quantified as
VDAC Slew Rate Programming Capacitor C
The slew rate of VDAC down-slope SR
(8), where I
slope.
The resistor R
Over Current Setting Resistor R
The inductor DC resistance is utilized to sense the inductor current. The copper wire of inductor has a constant
temperature coefficient of 3850 ppm/° C, and therefore the maximum inductor DCR can be calculated from (10),
where R
T_
The total input offset voltage (V
(V
sense resistor R
The over-current limit is set by the external resistor R
peak to peak ripple of the net inductor current is much smaller than the stand alone phase due to interleaving.
The ratio of the peak to average current in this case can be approximated using (13).
CS_OFST)
ROOM
Page 25 of 34
L_MAX
respectively.
SINK
of the amplifier itself and that created by the amplifier input bias current flowing through the current
VDAC
and R
CS
is the sink current of VDAC pin. The slew rate of VDAC up-slope is the same as that of down-
.
is used to compensate VDAC circuit and can be calculated as follows
L_ROOM
TD
TD
TD
TD
V
t
C
R
R
OCDEL
CS
VDAC
VDAC
L
_
2
4
5
3
_
MAX
=
=
TOFST
=
=
C
C
=
are the inductor DCR at maximum temperature T
=
=
C
C
SS
SS
0
=
SR
CS_TOFST
5 .
SS
C
OCSET
SS
/
I
/
I
R
=
DEL
DEL
CHG
SINK
DOWN
+
/
SS
L
/
V
DEL
DEL
_
3
I
CS
/
I
ROOM
DEL
2 .
1 *
*
DISCHG
C
CHG
DOWN
I
_
( *
V
VDAC
*
CHG
∗
OFST
1 .
=
I
DAC
10
3 (
*
) of current sense amplifier in phase ICs is the sum of input offset
. 3
CHG
=
44
SR
∗
. 0
−
92
2
−
1 [
C
15
+
−
12
VDAC
can be programmed by the external capacitor C
*
52
DOWN
1
SS
1
10
+
I
−
4 .
1 .
CSIN
5 .
3850
/
−
=
DEL
) 3
*
6
−
=
10
and Resistor R
+
C
t
1
−
C
OCDEL
1 *
OCSET
) 1 .
∗
*
−
SS
SS
TD
55
6
10
R
1 .
/
CS
/
DEL
=
DEL
−
52
*
4
6
10
C
∗
5 .
=
is determined by the value of C
and is given by (12). In a multiphase architecture the
*
52
*
(
SS
*
T
−
C
. 0
V
10
6
L
5 .
/
DAC
52
SS
12
DEL
_
−
MAX
*
/
6
5 .
DEL
10
VDAC
−
*
*
1
0
−
−
10
1 .
*
6
7 .
T
. 0
ROOM
−
6
92
−
)]
TD
4
L_MAX
(6)
(4)
(5)
(3)
(8)
(9)
(10)
(11)
and room temperature
July 03, 2008
VDAC
SS/DEL
IR3500V
(7)
as defined in
and can be