ir3084a International Rectifier Corp., ir3084a Datasheet
ir3084a
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ir3084a Summary of contents
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... DESCRIPTION The IR3084A Control IC combined with an IR XPhase way to implement a complete VR10 or VR11 power solution. The “Control” IC provides overall system control and interfaces with any number of “Phase” ICs which each drive and monitor a single phase of a multiphase converter. The XPhase expensive, and easier to design while providing higher efficiency than conventional approaches ...
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... IR3084A I SOURCE SINK 1mA 1mA 1mA 1mA 10mA 1mA 1mA 1mA 1mA 1mA 1mA 1mA 1mA 1mA 1mA 5mA 5mA 1mA 1mA 20mA 5mA 5mA 10mA 1mA ...
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... VIDSEL FLOATING Measure V(FB) – V(VSETPT) per test circuit in Figure 1. Applies to TBS VID codes. Note 2. Note 1 Note 1 45 deg Phase Shift, Note 1 Note 1 VBIAS–VEAOUT (ref. to VBIAS) Normal operation or Fault mode V(VDRP) – V(IIN), 0.5V 0.5V 0.5V Note 1 Note 1 IR3084A V 16V, 0.3V VOSNS 0.3V, CC MIN TYP MAX 0.5 0 ...
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... SS/DEL Discharge Comparator Threshold ENABLE INPUT Threshold Voltage ENABLE rising Threshold Voltage ENABLE falling Threshold Hysteresis Input Resistance Noise Pulse < 250ns will not register Blanking Time an ENABLE state change. Note 1 Page TEST CONDITION 5mA IR3084A MIN TYP MAX UNIT µ A 2.0 0.2 1.0 5.6 12.5 19.4 K 0.20 0.35 ...
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... VDAC ISINK VDAC BUFFER IOFFSET IOCSET IROSC IROSC AMP ROSC BUFFER CURRENT AMP + SOURCE GENERATOR - ROSC + 1.2V - VOSNS- Figure 1 – System Set Point Test Circuit IR3084A MIN TYP MAX 150 300 0 10 450 500 550 112 ...
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... Open Collector output that drives low during Start-Up and any external fault 27 VRRDY condition. Connect external pull-up. Enable Input. A logic low applied to this pin puts the IC into Fault mode. This pin 28 ENABLE has a 100K pull-down resistor to GND. Page IR3084A DESCRIPTION 10/30/2006 ...
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... PHASE FAULT CURRENT SHARE IR3086 PHASE IC CCS RCS PHASE FAULT CURRENT SHARE IR3086 PHASE IC CCS RCS ADDITIONAL PHASES Figure 2 – System Block Diagram IR3084A VR READY PHASE FAULT VR HOT VR FAN CIN VOUT SENSE+ VOUT+ COUT VOUT- VOUT SENSE- INPUT/OUTPUT 10/30/2006 ...
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... GENERATOR RAMPIN- EAIN RRAMP2 PWMRMP RAMP SLOPE RPWMRMP ADJUST SCOMP CPWMRMP SHARE CSCOMP ADJUST ERROR AMP + ISHARE 10K - DACIN Figure 3 – IR3084A PWM Block Diagram IR3084A PHASE IC PWM LATCH GATEH S PWM RESET COMPARATOR DOMINANT - R GATEL + ENABLE + O% DUTY - CYCLE RAMP COMPARATOR DISCHARGE ...
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... An additional advantage is that differences in ground or input voltage at the phases have no effect on operation since the PWM ramps are referenced to VDAC. Page 50% RAMP DUTY CYCLE SLOPE = 80mV / % DC SLOPE = 1.6mV / ns @ 200kHz SLOPE = 8.0mV / ns @ 1MHz Figure 4 – 8 Phase Oscillator Waveforms IR3084A 10/30/2006 ...
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... DUE TO LOAD DUE TO VIN INCREASE INCREASE (FEED-FORWARD) Figure 5 – PWM Operating Waveforms IR3084A ) BODY DIODE DUTY CYCLE DECREASE DUE TO LOAD DECREASE (BODY BRAKING) OR FAULT (VCC UV, VCCVID UV, OCP, VID=11111X 10/30/2006 STEADY-STATE OPERATION ...
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... PWM ramp thereby increasing its duty cycle and output current. The crossover frequency of the current share loop can be programmed with a capacitor at the SCOMP pin so that the share loop does not interact with the output voltage loop. Page CSA CO IR3084A 10/30/2006 ...
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... SET VR10 DAC SET VR11 DAC SET VID = 1.1V BOOT 1.24V VBIAS REGULATOR VBIAS - 6.9V + IROSC ROSC VCC BUFFER CURRENT AMP + SOURCE GENERATOR - Figure 7 – IR3084A Block Diagram IR3084A UVLO DISABLE FAULT OVER CURRENT S NO CPU 0. CPU LATCHED SS/DEL - FAULT 0.35V LATCH - S + ...
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... IR3084A VID1 VID0 VID5 VID6 Voltage 1.20000 1.19375 1.18750 1.18125 1.17500 ...
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... Table 2 – VR11 VID Table (Part 1) IR3084A Dec (VID7:VID0) Voltage 01000000 1.21250 01000001 1.20625 01000010 1.20000 01000011 1.19375 01000100 1.18750 01000101 1.18125 01000110 1.17500 01000111 1.16875 01001000 1.16250 01001001 1.15625 01001010 1 ...
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... F5 0.47500 F6 0.46875 F7 0.46250 F8 0.45625 F9 0.45000 FA 0.44375 FB 0.43750 FC 0.43125 FD 0.42500 FE 0.41875 FF Table 2 – VR11 VID Table (Part 2) IR3084A Dec (VID7:VID0) Voltage 11000000 0.41250 11000001 0.40625 11000010 0.40000 11000011 0.39375 11000100 0.38750 11000101 0.38125 11000110 0.37500 11000111 0.36875 11001000 0.36250 11001001 0.35625 11001010 0 ...
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... The IR3084A can accept changes in the VID code while operating and vary the DAC voltage accordingly. The sink/source capability of the VDAC buffer amp is programmed by the same external resistor that sets the oscillator frequency. The slew rate of the voltage at the VDAC pin can be adjusted by an external capacitor between VDAC pin and the VOSNS compensate the VDAC buffer amplifier ...
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... Start-up Modes The IR3084A has a programmable soft-start function to limit the surge current during the converter start-up. A capacitor connected between the SS/DEL and LGND pins controls soft start as well as over-current protection delay and hiccup mode timing. A charge current of 70uA controls the positive slope of the voltage at the SS/DEL pin ...
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... Table 3: 3084A Controller Functionality versus VIDSEL Voltages Page VIDSEL is connected to VBIAS (6.9V VCC 1.1V Boot VID Voltage During Table Startup? VR10 YES VR11 YES VR11 NO VR10 NO IR3084A VIDSEL is either floating or Ignore NO CPU Latch NO CPU Codes During Fault Code? Startup? YES YES YES YES 10/30/2006 ...
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... SOFT START TIME SAMPLE 1.3ms (TD4+TD5) 1.6ms (TD2) DELAY 1.0ms (TD3) DYNAMIC VID TIME 200us (TD4) VID SETTING SOFT START TIME VR_RDY DELAY 1.6ms 2.3ms IR3084A 9.1V UVLO VDAC NORMAL POWER-DOWN OPERATION (VCC UVL INITIATES FAULT MODE) 9.1V UVLO POWER-DOWN (VCC UVL NORMAL ...
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... The SS/DEL capacitor will discharge down to 0.215V through a 6.5uA current source. If the fault has cleared the fault latch will be reset by the discharge comparator allowing a normal start-up sequence to occur VID = FAULT condition is latched it can only be cleared by cycling power to the IR3084A on and off. OveríCurrent Protection Delay and Hiccup Mode Figure 11 depicts the operating waveforms of the Over-Current protection ...
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... Error Amplifier’s output voltage. When the IR3084A is in UVLO, the Error Amplifier is disabled and EAOUT very low voltage (<200mV) thus preventing the Phase ICs from becoming active. During power-up, the IR3084A’s fault latch is reset when VCC exceeds 9.9V if there are no other faults. If the VCC voltage drops below 9.1V the fault latch will be set. ...
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... System Reference Voltage (VBIAS) The IR3084A supplies a 6.9V/6mA precision reference voltage from the VBIAS pin. The oscillator ramp trip points are based on the VBIAS voltage so it should be used to program the Phase ICs phase delay to minimize phase errors. Phase IC Gate Driver Bias Regulator / VRHOT Comparator ...
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... I(VDAC SOURCE) (uA) I(VDAC SINK) (uA) 150 100 1.E+01 IR3084A Figure 14: I(OCSET) versus ROSC ROSC (Kohms) Figure 16: I(REGSET) CURRENT versus ROSC ROSC (Kohms) Figure 18: IR3084 Error Amplifier Bode Plot 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 ...
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... OCSET +12V 12.7K 21 VCC 12 VDAC R31 C131 10 26 ROSC1 30.1K 0.1uF SS/DEL 11 ROSC CSS/DEL1 0.1uF 22 VOSNS-- LGND 10 Figure 19 – IR3084A/3086A 5 Phase VRM/EVRD 11 Converter Page R1332 Q6 1 CJD200 C205 C137 0.1uF 1uF R138 2K C136 C90 0.1uF 100pF RVGDRV1 CVGDRV1 97.6K 10nF RVDAC1 3.5 CVDAC1 33nF ...
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... DESIGN PROCEDURES – IR3084A and IR3086A Chipset IR3084A EXTERNAL COMPONENTS Oscillator Resistor Rosc The oscillator of IR3084A generates a triangle waveform to synchronize the phase ICs, and the switching frequency of the each phase converter equals the oscillator frequency, which is set by the external resistor R according to the curve in Figure 13 on page 23. ...
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... IC is the sum of input offset ) ( ) ∗ − ∗ − − CSIN CS CSIN CS , see Figure 15 on page 23. OSC + C IR3084A DRP voltage and output voltage at no load. DAC ( TOFST CSA OS_EA = − ...
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... SS DEL − − − DEL TD 4 − 100 DEL − IR3084A SS/DEL ) from the data CHG * TD 2 (9) RFB + RDRP ). (10) ). (11) V − (12) (13) 10/30/2006 . ...
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... OCSET pin, changes with switching frequency setting G ∗ ∗ CS_TOFST I OCSET ∗ ∗ ∗ /( IR3084A L_MAX (14) is calculated from Equation (15). IC_MAX )] (15) is the ratio of inductor peak current MIN (16) (17) 10/30/2006 and room is the LIMIT ...
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... V ) ln(V IN DAC and Resistors R and R CS+ CS+ . Pre select the capacitor C L The resistor R is determined by the ratio of the bias current from the . CS ¢ value is needed. CS+ IR3084A should be connected to RAMP − − DAC PWMRMP CS ¡ and capacitor CS+ and calculate R CS+ (19) ...
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... If the resistor R determined as: ∗ PHASEx PHASEx1 R PHASEx2 − PHASEx Page and R HOTSET1 HOTSET2 + 1.241 is pre selected, R HOTSET1 HOTSET2 and R PHASE1 PHASE2 PHASEx1 IR3084A (ºC) of phase IC. J (21) can be calculated as follows. (22) is pre-selected, the resistor R PHASEx2 (23) 10/30/2006 is ...
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... PHASEx and R and connect RMPIN+ or RMPIN PHASEx2 , PHASEx1 ∗ ∗ PHASEx BIAS PHASEx1 − V BIAS HOTSET *R PHASEx1 HOTSET IR3084A R and R PHASE1, PHASE2 PHASE3 and R and connect HOTSET pin PHASEx2 then calculate R and R PHASEx2 PHASEx3, (24) (25) PHASEx between R PHASEx2 (26) (27) 10/30/2006 ...
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... Page CCP1 VO+ CCP RFB1 - VDRP EAOUT EAOUT + (b) Type III compensation C can be determined by Equations (28) and (29). CP and PWMRMP IR3084A CCP1 RFB RCP CCP CFB FB - EAOUT EAOUT VDAC RDRP + CDRP (28) (29) 10/30/2006 is CP1 ...
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... PWMRMP FB1 and determine the C C SCOMP + * * * * * CS_ROOM 1. PWMRMP − DAC I DAC IR3084A (31) and R from Equations (32) and (33). DRP (32) (33) ) based on the (35) 10/30/2006 (30) (34) ...
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... SW Output Inductors 220 nH Output Capacitors 560uF IR3084A EXTERNAL COMPONENTS Oscillator Resistor Rosc The switching frequency sets the value of R the switching frequency of 400kHz per phase requires R VDAC Slew Rate Programming Capacitor C From Figure 17 on page 23, the sink current of the VDAC pin at 400kHz (R VDAC slew-rate programming capacitor from the specified negative slew rate using Equation (1) ...
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... 3984 . 0 1710 . 0 0195 . 0 00494 = 123 5 . ohms − IR3084A ) = and R , respectively. For this CS+ CS £ is found to be 6.19K . bias currents are determined to be 0.25µA ) Ω 574 mV VSETPT bias current is determined to be 40µA at − ...
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... V − = − − − − 100 * 250 − IR3084A = 787 1 . ohms − 0988 uF or 0.1uF 324 + 787 − 324 + − ...
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... ∗ MIN ( CS_TOFST I OCSET − + ∗ 3 273 . 0 574 * IR3084A − − ∗ + ∗ − 3850*10 (100 25)] − ∗ − ∗ − 1470*10 (101 25)] =30.1k OSC − ∗ ∗ ∗ 220 * 10 12 ...
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... and R HOTSET1 HOTSET2 − ∗ 241 . 116 . 1 241 J ∗ Ω − IR3084A PWMRMP − − DAC PWMRMP = 15.8k , − − ln(12 1.30 0.8)] CS ¤ = 6.19k CS ¥ choose R =20.0k HOTSET1 10/30/2006 and using CS ¥ ...
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... FB PWMRMP − − 220 * 560 * Ω 162 Choose R =162 FB1 162 IR3084A Ω PHASE32 − − 220 * 560 * − − − 015 130 Choose C CP ...
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... O CI − π − π − 130 IR3084A =4kHz and calculate FMI and − 400 * 0105 − − − ...
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... SS/DEL Page OSC OCSET VDAC VDAC VCC LGND VSETPT REGFB OCSET REGDRV VDAC REGSET ROSC SS/DEL VOSNS- VRRDY VID0 ENABLE VID1 To SYSTEM IR3084A , C and R . Avoid using any SS/DEL CC/DEL R SETPT R OCSET R VDAC R OSC C VDAC To Voltage Remote Sense 10/30/2006 ...
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... Ensure that the solder resist in between the lead lands and the pad land is aspect ratio of the solder resist strip separating the lead lands from the pad land. • The single via in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm larger than the diameter of the via. Page IR3084A 10/30/2006 ...
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PCB METAL AND COMPONENT PLACEMENT • Lead land width should be equal to nominal part lead width. The minimum lead to lead spacing should be • Lead land length should be equal to maximum part lead length + 0.2 mm ...
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STENCIL DESIGN • The stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. Reducing the amount of solder deposited will minimize the occurrence of lead shorts. Since for 0.5mm pitch devices the ...
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PACKAGE INFORMATION 28L MLPQ ( Body) – WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252 7105 www.irf.com Page &: C/W JC ...