ltc1876eg-trpbf Linear Technology Corporation, ltc1876eg-trpbf Datasheet - Page 25

• Manufacturer Part Number: ltc1876eg-trpbf
• Description: High Efficiency, 2-phase, Dual Synchronous Step-down Switching Controller And Step-up Regulator
• Manufacturer: Linear Technology Corporation

APPLICATIO S I FOR ATIO
quadrupling the importance of loss terms in the switching
regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and only when operating at high input voltages (typically
20V or greater). Transition losses can be estimated from:
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses in the
design of a system. The internal battery and fuse resis-
tance losses can be minimized by making sure that C
adequate charge storage and very low ESR at the switch-
ing frequency. A 25W supply will typically require a
minimum of 20 F to 40 F of capacitance having a maxi-
mum of 20m to 50m of ESR. The LTC1876 step-down
controllers 2-phase architecture typically halves this input
capacitance requirement over competing solutions. Other
losses including Schottky conduction losses during dead-
time and inductor core losses generally account for less
than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
amount equal to I
series resistance of C
discharge C
forces the regulator to adapt to the current change and
return V
time V
ringing, which would indicate a stability problem. OPTI-
LOOP compensation allows the transient response to be
optimized over a wide range of output capacitance and
ESR values. The availability of the I
optimization of control loop behavior but also provides a
DC coupled and AC filtered closed loop response test
point. The DC step, rise time and settling at this test point
truly reflects the closed loop response . Assuming a pre-
dominantly second order system, phase margin and/or
Transition Loss = (1.7) V
OUT
OUT
can be monitored for excessive overshoot or
OUT
to its steady-state value. During this recovery
generating the feedback error signal that
LOAD
U
OUT
(ESR), where ESR is the effective
. I
U
IN
LOAD
2
I
O(MAX)
also begins to charge or
TH
W
pin not only allows
C
RSS
OUT
f
shifts by an
U
IN
has
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The I
external components shown in the Figure 1 circuit will
provide an adequate starting point for most applications.
The I
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to maximize
transient response once the final PC layout is done and the
particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
feedback factor gain and phase. An output current pulse of
20% to 100% of full-load current having a rise time of 1 s
to 10 s will produce output voltage and I
that will give a sense of the overall loop stability without
breaking the feedback loop. The initial output voltage step
resulting from the step change in output current may not
be within the bandwidth of the feedback loop, so this signal
cannot be used to determine phase margin. This is why it
is better to look at the I
feedback loop and is the filtered and compensated control
loop response. The gain of the loop will be increased by
increasing R
increased by decreasing C
factor that C
the same, thereby keeping the phase the same in the most
critical frequency range of the feedback loop. The output
voltage settling behavior is related to the stability of the
closed-loop system and will demonstrate the actual over-
all supply performance.
A second, more severe transient is caused by switching in
loads with large (>1 F) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
should be controlled so that the load rise time is limited to
approximately 25 • C
require a 250 s rise time, limiting the charging current to
about 200mA.
LOAD
TH
OUT
to C
series R
, causing a rapid drop in V
OUT
C
C
is decreased, the zero frequency will be kept
is greater than 1:50, the switch rise time
and the bandwidth of the loop will be
C
-C
C
LOAD
filter sets the dominant pole-zero
C
. Thus a 10 F capacitor would
TH
. If R
pin signal which is in the
C
is increased by the same
OUT
. No regulator can
TH
LTC1876
pin waveforms
25
1876fa
TH