ltc1064-1csw-trpbf Linear Technology Corporation, ltc1064-1csw-trpbf Datasheet - Page 6

• Manufacturer Part Number: ltc1064-1csw-trpbf
• Description: Low Noise, Fast, Quad Universal Filter Building Block
• Manufacturer: Linear Technology Corporation

LTC1064
6
PIN
V
bypassed with a 0.1µF ceramic capacitor. Low noise,
nonswitching power supplies are recommended. The de-
vice operates with a single 5V supply and with dual
supplies. The absolute maximum operating power supply
voltage is ±8V.
CLK (Pin 18): Clock. For ±5V supplies the logic threshold
level is 1.4V. For ±8V and 0V to 5V supplies the logic
threshold levels are 2.2V and 3V respectively. The logic
threshold levels vary ±100mV over the full military tem-
perature range. The recommended duty cycle of the input
clock is 50%, although for clock frequencies below 500kHz,
the clock “on” time can be as low as 200ns. The maximum
clock frequency for ±5V supplies is 4MHz. For ±7V
supplies and above, the maximum clock frequency is
7MHz.
+
, V
U
–
FUNCTIONS
(Pins 7, 19): Power Supplies. They should be
U
NOTE: PINS 5, 8, 20, IF NOT USED, SHOULD BE CONNECTED TO PIN 6
U
1µF
+
GROUND
ANALOG
PLANE
V
+
5k
5k
V+/2
0.1µF
Figure 1. Single Supply Operation
10
11
12
1
2
3
4
5
6
7
8
9
AGND
V
+
LTC1064
50/100
CLK
V
–
AGND (Pin 6): Analog Ground. When the LTC1064 oper-
ates with dual supplies, Pin 6 should be tied to system
ground. When the LTC1064 operates with a single positive
supply, the analog ground pin should be tied to 1/2 supply
and it should be bypassed with a 1µF solid tantalum in
parallel with a 0.1µF ceramic capacitor, Figure 1. The
positive input of all the internal op amps, as well as the
common reference of all the internal switches, are inter-
nally tied to the analog ground pin. Because of this, a very
“clean” ground is recommended.
50/100 (Pin 17): By tying Pin 17 to V
operate with a clock-to-center frequency ratio internally
set at 50:1. When Pin 17 is at mid-supplies, sections B and
C operate with (f
operate at 100:1. When Pin 17 is shorted to the negative
supply pin, all filter sections operate with (f
100:1.
24
23
22
21
20
19
18
17
16
15
14
13
1064 F01
CLK
/f
O
TO DIGITAL
GROUND
) = 50:1 and sections A and D
CLOCK INPUT
V
V
V
+
+
+
= 15V, TRIP VOLTAGE = 7V
= 10V, TRIP VOLTAGE = 6.4V
= 5V, TRIP VOLTAGE = 3V
+
, all filter sections
CLK
/f
O
1064fb
) =