ltc1069-7is8-trpbf Linear Technology Corporation, ltc1069-7is8-trpbf Datasheet - Page 6

• Manufacturer Part Number: ltc1069-7is8-trpbf
• Description: Low Power, 8th Order Progressive Elliptic, Lowpass Filter
• Manufacturer: Linear Technology Corporation

APPLICATIONS
LTC1069-1
PIN
NC (Pins 3, 6): No Connection. Pins 3 and 6 are not
connected to any internal circuity; they should be prefer-
ably tied to ground.
V
connected to the inverting input of an op amp through a
43k resistor.
CLK (Pin 5): Clock Input Pin. Any TTL or CMOS clock
source with a square wave output and 50% duty cycle
( 10%) is an adequate clock source for the device. The
power supply for the clock source should not necessarily
be the filter’s power supply. The analog ground of the filter
should be connected to clock’s ground at a single point
only. Table 1 shows the clock’s low and high level thresh-
old value for a dual or a single supply operation. A pulse
generator can be used as a clock source provided the high
level ON time is greater than 0.42 s (V
waves less than 100kHz are not recommended for clock
signal because excessive slow clock rise or fall times
generate internal clock jitter. The maximum clock rise or
Temperature Behavior
The power supply current of the LTC1069-1 has a positive
temperature coefficient. The GBW product of its internal
op amps is nearly constant and the speed of the device
does not degrade at high temperatures. Figures 3a, 3b and
3c show the behavior of the maximum passband of the
device for various supplies and temperatures. The filter,
6
IN
–0.5
–1.0
–1.5
–2.0
U
2.0
1.5
1.0
0.5
(Pin 4): Filter Input Pin. The filter input pin is internally
0
0.5
FUNCTIONS
V
f
V
CLK
S
IN
1.5
= 3.3V
= 0.5V
= 750kHz
U
2.5
RMS
FREQUENCY (kHz)
T
3.5
A
Figure 3a
= 85 C
U
U
T
A
4.5
T
= –40 C
A
= 25 C
INFORMATION
U
5.5
6.5
1069-1 F03a
7.5
W
S
–0.5
–1.0
–1.5
–2.0
= 5V). Sine
2.0
1.5
1.0
0.5
0
0.5
U
V
f
V
CLK
1.5
S
IN
= 5V
= 1.2V
= 1MHz
2.5
RMS
3.5
FREQUENCY (kHz)
4.5
Figure 3b
T
fall is 1 s. The clock signal should be routed from the right
side of the IC package to avoid coupling into any input or
output analog signal path. A 1k resistor between the clock
source and the clock input pin (5) will slow down the rise
and fall times of the clock to further reduce charge cou-
pling, Figure 1.
Table 1. Clock Source High and Low Thresholds
POWER SUPPLY
Dual Supply = 5V
Single Supply = 10V
Single Supply = 5V
Single Supply = 3.3V
V
filter and it can source or sink 1mA. Driving coaxial cables
or resistive loads less than 20k will degrade the total
harmonic distortion of the filter. When evaluating the
device’s dynamic range, a buffer is required to isolate the
filter’s output from coax cables and instruments.
especially at 5V supply, has a passband behavior which
is nearly temperature independent.
Clock Feedthrough
The clock feedthrough is defined as the RMS value of the
clock frequency and its harmonics that are present at the
filter’s output pin (8). The clock feedthrough is tested with
5.5
A
OUT
= 85 C
6.5
T
(Pin 8): Filter Output Pin. Pin 8 is the output of the
A
7.5 8.5 9.5 10.5
= –40 C
T
A
= 25 C
1069-1 F03b
–0.5
–1.0
–1.5
–2.0
2.0
1.5
1.0
0.5
0
1
HIGH LEVEL
V
f
V
CLK
S
IN
= 5V
3
1.5V
6.5V
1.5V
1.2V
= 2V
= 1.5MHz
RMS
5
FREQUENCY (kHz)
Figure 3c
7
T
A
= 25 C
9
LOW LEVEL
0.5V
5.5V
0.5V
0.5V
11
T
A
T
A
= –40 C
= 85 C
13
1069-1 F03c
15