st52f510 STMicroelectronics, st52f510 Datasheet - Page 97

• Manufacturer Part Number: st52f510
• Description: 8-bit Intelligent Controller Unit Icu Two Timer/pwms, Adc, I2c, Spi, Sci
• Manufacturer: STMicroelectronics

Figure 15.2 Serial Peripheral Interface Block Diagram
Procedure
– Select the SPR0, SPR1 and SPR2 bits to define
– Select the CPOL and CPHA bits to define one of
– The SS pin must be connected to a high level
– The MSTR and SPE bits must be set (they re-
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Transmit sequence
Transmit sequence begins when a byte is written in
the SPI_OUT register.
the serial clock baud rate (see SPI_CR register).
the four relationships between the data transfer
and the serial clock (see Figure 15.4).
signal during the complete byte transmit se-
quence.
main set only if the SS pin is connected to a high
level signal).
MOSI
MISO
SCK
SS
8-Bit Shift Register
Read
Read Buffer
Write
CONTROL
SERIAL
CLOCK
GENERATOR
MASTER
Internal Bus
SPI_OUT
SPI_IN
The data byte is loaded in parallel into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if the SPIE bit is set.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the SPI_IN register is
read, the SPI peripheral returns this buffered
value. Clearing the SPIF bit is performed by the
following software sequence:
1. An access to the SPI_STATUS_CR register
2. A read to the SPI_IN register.
Note: While the SPIF bit is set, all writes to the
SPI_OUT
SPI_STATUS_CR register is read.
while the SPIF bit is set
SPIE
SPIF WCOL
SPE
register
CONTROL
SPR2
STATE
SPI
OR
MSTR
are
MODF
ST52F510/F513/F514
CPOL
inhibited
-
SPI_STATUS_CR
CPHA
SOD
SPR1
SSM
request
until
IT
SPI_CR
SPR0
SSI
97/106
the