tr1d4a Centellax, tr1d4a Datasheet

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tr1d4a

Manufacturer Part Number
tr1d4a
Description
40g Clock And Data Demultiplexer
Manufacturer
Centellax
Datasheet
The Centellax TR1D4A is a small high-performance 3.5-44Gb/s clock and data demultiplexer, designed to sim-
plify the process of making high-bitrate BER measurements at half- or quarter-rate speeds. The TR1D4A is
capable of operating in demux-by-2 (17Gb/s to 8.5Gb/s) or demux-by-4 (38Gb/s to 9.5Gb/s) modes, with an
adjustable sub-rate clock output for triggering BER testers, oscilloscopes, logic analyzers, or other instruments.
Input Bit Rate**
Output Bit Rate
Data Input Amplitude*
Data Output Amplitude
Clock Input Amplitude
Clock Output Amplitude**
Demux-by-4 Clock Input Frequency
Demux-by-2 Clock Input Frequency
*Data input uses a V (f) connector. Data output and clock input use K (f) connectors. Clock output uses an SMA(f) connector.
**Differential input/output, can be used single-ended with proper 50ohm termination.
***Maximum input bit rate is 22Gb/s.
Specifications subject to change without notice. Copyright © 2001-2009 Centellax, Inc. Printed in USA. 11 Jun 2009. smd-00029 rev A.
CENTELLAX
40G Clock and Data Demultiplexer
,
**
• Web: http://www.centellax.com/ • Email: sales@centellax.com • Tel: 866.522.6888 • Fax: 707.568.7647
mVpp-se
mVpp-se
mVpp
mVpp
Gb/s
Gb/s
GHz
GHz
0.875
1.75
150
210
470
3.5
3.5
-
600
240
600
500
-
-
-
-
• Clock and data demultiplexer for
• 3.5 - 44Gb/s operation
• Demux-by-2 or demux-by-4
• Integrated phase shifter for high-
• Differential or single-ended input
• Adjustable sub-rate clock output
1200
1000
270
22
44
11
22***
lower-rate BER measurements
speed clock and data alignment
-
CENTELLAX

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tr1d4a Summary of contents

Page 1

... Clock and Data Demultiplexer The Centellax TR1D4A is a small high-performance 3.5-44Gb/s clock and data demultiplexer, designed to sim- plify the process of making high-bitrate BER measurements at half- or quarter-rate speeds. The TR1D4A is capable of operating in demux-by-2 (17Gb/s to 8.5Gb/s) or demux-by-4 (38Gb/s to 9.5Gb/s) modes, with an adjustable sub-rate clock output for triggering BER testers, oscilloscopes, logic analyzers, or other instruments. ...

Page 2

... Operation: 1. Split the clock output of the clock source. 2. One output of the splitter to the TG2P1A clock input. 3. The other output to the TR1D4A Clock In1. 20G Operation: 1. TG1P2A Clk/1 to Clock In1. 2. Loop Loop C to Clock In2. 4. Loop UXD20PEs 1 and 2’s ratios = ½ and 3 and 4’s ratio = 1. ...

Page 3

... PRBS clock and data demultiplexer; includes standard 1-year warranty. • Web: http://www.centellax.com/ • Email: sales@centellax.com • Tel: 866.522.6888 • Fax: 707.568.7647 CENTELLAX Specifications subject to change without notice. Copyright © 2001-2009 Centellax, Inc. Printed in USA. 11 Jun 2009. smd-00029 rev A. ...

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