mcf52258 Freescale Semiconductor, Inc, mcf52258 Datasheet - Page 30

• Manufacturer Part Number: mcf52258
• Description: Mcf52259 Coldfire Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Electrical Characteristics
1
2
3
4
5
6
7
8
9
10
2.8
2.9
A multi-function external bus interface called Mini-FlexBus is provided with basic functionality to interface to slave-only
devices up to a maximum bus frequency of 80MHz. It can be directly connected to asynchronous or synchronous devices such
as external boot ROMs, flash memories, gate-array logic, or other simple target (slave) devices with little or no additional
circuitry. For asynchronous devices a simple chip-select based interface can be used.
All processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect to the rising edge of
a reference clock, MB_CLK. The MB_CLK frequency is half the internal system bus frequency.
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the Mini-FlexBus output
clock (MB_CLK). All other timing relationships can be derived from these values.
30
Frequency un-LOCK range
Frequency LOCK range
CLKOUT period jitter
On-chip oscillator frequency
• Peak-to-peak (clock edge to clock edge)
• Long term (averaged over 2 ms interval)
In external clock mode, it is possible to run the chip directly from an external clock source without enabling the PLL.
All internal registers retain data at 0 Hz.
Depending on packaging; see the orderable part number summary.
Loss of Reference Frequency is the reference frequency detected internally, which transitions the PLL into self clocked mode.
Self clocked mode frequency is the frequency at which the PLL operates when the reference frequency falls below f
default MFD/RFD settings.
This parameter is characterized before qualification rather than 100% tested.
Proper PC board layout procedures must be followed to achieve specifications.
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
synthesizer control register (SYNCR).
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via V
for a given interval.
Based on slow system clock of 40 MHz measured at f
Minimum core speed for USB operation
USB Operation
Mini-FlexBus External Interface Specifications
4, 5, 9 ,10
Characteristic
, measured at f
Table 13. Oscillator and PLL Specifications (continued)
Characteristic
DDPLL
(V
DD
Table 14. USB Operation Specifications
MCF52259 ColdFire Microcontroller, Rev. 1
and V
and V
SYS
SSPLL
DDPLL
Max
and variation in crystal oscillator frequency increase the C
= 3.0 to 3.6 V, V
sys
max.
SS
Symbol
C
f
f
= V
f
LCK
oco
UL
jitter
f
SSPLL
sys_USB_min
Symbol
= 0 V)
–0.75
–1.5
7.84
Min
—
—
Value
16
Freescale Semiconductor
Max
0.75
8.16
1.5
.01
10
MHz
Unit
jitter
percentage
sys
% f
LOR
% f
% f
MHz
Unit
.
sys
ref
ref
with