mcm67b618bfn9 Freescale Semiconductor, Inc, mcm67b618bfn9 Datasheet

mcm67b618bfn9

Manufacturer Part Number

mcm67b618bfn9

Description

64k X 18 Bit Burstram Synchronous Fast Static Ram With Burst Counter And Self-timed Write , Inc

Manufacturer

Freescale Semiconductor, Inc

Datasheet

1.MCM67B618BFN9.pdf (11 pages)

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MOTOROLA FAST SRAM

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

64K x 18 Bit BurstRAM

Synchronous Fast Static RAM

With Burst Counter and Self–Timed Write

memory designed to provide a burstable, high–performance, secondary cache

for the i486 and Pentium

65,536 words by 18 bits) is fabricated using Motorola’s high–performance

silicon–gate BiCMOS technology. The device integrates input registers, a 2–bit

counter, high speed SRAM, and high drive capability outputs onto a single

monolithic circuit for reduced parts count implementation of cache data RAM

applications. Synchronous design allows precise cycle control with the use of an

external clock (K). BiCMOS circuitry reduces the overall power consumption of

the integrated functions for greater reliability.

except output enable (G) are clock (K) controlled through positive–

edge–triggered noninverting registers.

or address status cache controller (ADSC) input pins. Subsequent

burst addresses can be generated internally by the MCM67B618B

(burst sequence imitates that of the i486 and Pentium) and controlled

by the burst address advance (ADV) input pin. The following pages pro-

vide more detailed information on burst controls.

edge of the clock (K) input. This feature eliminates complex off–chip

write pulse generation and provides increased flexibility for incoming

signals.

writeable bytes. LW controls DQ0 – DQ8 (the lower bits), while UW

controls DQ9 – DQ17 (the upper bits).

widths and cache memory. See Figure 2 for applications information.

i486 is a trademark and Pentium is a registered trademark of Intel Corp.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

REV 3

9/21/99

Motorola, Inc. 1999

The MCM67B618B is a 1,179,648–bit synchronous fast static random access

Addresses (A0 – A15), data inputs (D0 – D17), and all control signals

Bursts can be initiated with either address status processor (ADSP)

Write cycles are internally self–timed and are initiated by the rising

Dual write enables (LW and UW) are provided to allow individually

This device is ideally suited for systems that require wide data bus

Single 5 V 5% Power Supply

Fast Access Time: 9 ns Max

Byte Writeable via Dual Write Enables

Internal Input Registers (Address, Data, Control)

Internally Self–Timed Write Cycle

ADSP, ADSC, and ADV Burst Control Pins

Asynchronous Output Enable Controlled Three–State Outputs

Common Data Inputs and Data Outputs

3.3 V I/O Compatible

High Board Density 52–Lead PLCC Package

microprocessors. The MCM67B618B (organized as

DQ10

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ11

DQ9

V CC

V SS

21 22 23 24 25 26 27 28 29 30 31 32 33

7 6 5 4 3 2 1 52 51 50 49 48 47

All power supply and ground pins must be con-

nected for proper operation of the device.

A0 – A15

ADV

ADSC

ADSP

DQ0 – DQ17

V CC

V SS

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . .

MCM67B618B

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . .

. . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . .

PIN ASSIGNMENTS

. . . . . . . . .

. . . . . . . . . . . . . . . .

. . . . . . . . . .

FN PACKAGE

CASE 778–02

PIN NAMES

PLASTIC

Processor Address Status

Controller Address Status

Lower Byte Write Enable

Upper Byte Write Enable

Burst Address Advance

Order this document

+5 V Power Supply

by MCM67B618B/D

Data Input/Output

MCM67B618B

Address Inputs

No Connection

Output Enable

Chip Enable

Ground

Clock

DQ8

DQ7

DQ6

V CC

V SS

DQ5

DQ4

DQ3

DQ2

V SS

V CC

DQ1

DQ0

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mcm67b618bfn9 Summary of contents

Page 1

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Advance Information 64K x 18 Bit BurstRAM Synchronous Fast Static RAM With Burst Counter and Self–Timed Write The MCM67B618B is a 1,179,648–bit synchronous fast static random access memory designed to provide a burstable, high–performance, secondary cache ...

Page 2

K ADSC ADSP ADDRESS A0 – A15 REGISTER UW REGISTER DQ0 – DQ8 9 DQ9 – DQ17 All registers are positive–edge triggered. The ADSC or ADSP signals control the duration of the burst and the start ...

Page 3

SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3) E ADSP ADSC ADV ...

Page 4

DC OPERATING CONDITIONS AND CHARACTERISTICS ( 5 Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage * V IL (min) ...

Page 5

AC OPERATING CONDITIONS AND CHARACTERISTICS ( 5 Unless Otherwise Noted) Input Timing Measurement Reference Level . . . . . . . . . . . . . . ...

Page 6

KHADSX t KHKH K t KHKL t ADSVKH ADSP ADSC t KHAX t AVKH ADDRESS A1 LW KHEX t EVKH E ADV t KHQV t GLQV G t GLQX Q(A1) DATA OUT SINGLE READ NOTE: Q(A2) represents ...

Page 7

MOTOROLA FAST SRAM MCM67B618B 7 ...

Page 8

COMBINATION READ/WRITE CYCLE (E Low, ADSC High ADSVKH t KHADSX ADSP t AVKH t KHAX ADDRESS A1 LW, UW ADV G t KHQV DATA IN t KHQX1 DATA OUT MCM67B618B 8 t KHKH t KHKL t KLKH A2 ...

Page 9

... DATA ADDRESS Pentium CLK ADS CONTROL Using Four MCM67B618BFN9s with a 66 MHz Pentium Motorola Memory Prefix Part Number MOTOROLA FAST SRAM APPLICATION EXAMPLE DATA BUS ADDRESS BUS CLOCK ADDR K CACHE CONTROL LOGIC 512K Byte Burstable, Secondary Cache Figure 2 ORDERING INFORMATION (Order by Full Part Number) ...

Page 10

0.010 (0.25) T L– VIEW S MCM67B618B 10 PACKAGE DIMENSIONS FN PACKAGE 52–LEAD PLCC CASE 778–02 0.007 (0.18 BRK –M– ...

Page 11

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of ...

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