ltc3831egn-trpbf Linear Technology Corporation, ltc3831egn-trpbf Datasheet - Page 6

• Manufacturer Part Number: ltc3831egn-trpbf
• Description: High Power Synchronous Switching Regulator Controller For Ddr Memory Termination
• Manufacturer: Linear Technology Corporation

TYPICAL PERFORMANCE CHARACTERISTICS
LTC3831
TG ( Pin 1): Top Driver Output. Connect this pin to the
gate of the upper N-channel MOSFET, Q1. This output
swings from PGND to PV
or during shutdown mode.
PV
to a potential of at least V
can be generated using an external supply or a simple
charge pump connected to the switching node between
the upper MOSFET and the lower MOSFET.
PGND (Pin 3): Power Ground. Both drivers return to
this pin. Connect this pin to a low impedance ground in
close proximity to the source of Q2. Refer to the Layout
Consideration section for more details on PCB layout
techniques.
GND (Pin 4): Signal Ground. All low power internal cir-
cuitry returns to this pin. To minimize regulation errors
due to ground currents, connect GND to PGND right at
the LTC3831.
R
resistor divider that generate the internal ratiometric refer-
ence for the error amplifi er. The reference voltage is set
at 0.5 • (V
FB (Pin 6): Feedback Voltage. FB senses the regulated
output voltage either directly or through an external
PIN FUNCTIONS
6
–
, R
CC1
10
50
40
30
20
0
+
0
PV
vs Gate Capacitance
(Pin 2): Power Supply Input for TG. Connect this pin
T
(Pins 5, 7): These two pins connect to the internal
A
CC
GATE CAPACITANCE AT TG AND BG (nF)
= 25°C
1
R
Supply Current
+ – V
2
3
R
4
–).
PV
PV
5
CC1,2
CC1,2
6
= 12V
CC1
= 5V
IN
7
+ V
. It remains low if BG is high
8
GS(ON)(Q1)
3831 G20
9
10
. This potential
200
180
160
140
120
100
80
60
40
20
0
0
TG Rise/Fall Time
vs Gate Capacitance
T
A
GATE CAPACITANCE AT TG AND BG (nF)
= 25°C
1
2
t
r
AT PV
t
f
AT PV
3
CC1,2
4
CC1,2
t
= 5V
resistor divider. The FB pin is servoed to the ratiometric
reference under closed-loop conditions. The LTC3831 can
operate with a minimum V
of (V
SHDN (Pin 8): Shutdown. A TTL compatible low level at
SHDN for longer than 100μs puts the LTC3831 into shut-
down mode. In shutdown, TG and BG go low, all internal
circuits are disabled and the quiescent current drops to
10μA max. A TTL compatible high level at SHDN allows
the part to operate normally. This pin also double as an
external clock input to synchronize the internal oscillator
with an external clock.
SS (Pin 9): Soft-Start. Connect this pin to an external
capacitor, C
LTC3831 goes into current limit, C
reduce the duty cycle. C
during power-up, the current through Q1 will not exceed
the current limit level.
COMP (Pin 10): External Compensation. This pin internally
connects to the output of the error amplifi er and input of
the PWM comparator. Use a RC + C network at this pin
to compensate the feedback loop to provide optimum
transient response.
5
r
AT PV
= 5V
t
f
6
AT PV
CC1,2
CC
7
CC1,2
= 12V
– 1.75V).
8
= 12V
SS
3831 G21
9
, to implement a soft-start function. If the
10
2A/DIV
50mV/
I
V
LOAD
OUT
DIV
SS
Transient Response
FB
must be selected such that
of 1.1V and maximum V
SS
50μs/DIV
is discharged to
3831fa
3831 G22
FB