ltc3728legn-trpbf Linear Technology Corporation, ltc3728legn-trpbf Datasheet - Page 26

• Manufacturer Part Number: ltc3728legn-trpbf
• Description: Dual, 550khz, 2-phase Synchronous Step-down Switching Regulator
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
LTC3728
each R
R
losses), then the total resistance is 130mΩ. This results
in losses ranging from 3% to 13% as the output current
increases from 1A to 5A for a 5V output, or a 4% to 20%
loss for a 3.3V output. Effi ciency varies as the inverse
square of V
output power level. The combined effects of increasingly
lower output voltages and higher currents required by
high performance digital systems is not doubling but
quadrupling the importance of loss terms in the switching
regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become signifi cant only when operating at high input
voltages (typically 15V or greater). Transition losses can
be estimated from:
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% effi ciency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
losses can be minimized by making sure that C
equate charge storage and very low ESR at the switching
frequency. A 25W supply will typically require a minimum of
20μF to 40μF of capacitance having a maximum of 20mΩ to
50mΩ of ESR. The LTC3728 2-phase architecture typically
halves this input capacitance requirement over competing
solutions. Other losses including Schottky conduction
losses during dead-time and inductor core losses generally
account for less than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
26
ESR
Transition Loss = (1.7) V
= 40mΩ (sum of both input and output capacitance
DS(ON)
OUT
= 30mΩ, R
for the same external components and
L
= 50mΩ, R
IN
2
I
O(MAX)
SENSE
C
RSS
= 10mΩ and
f
IN
has ad-
load current. When a load step occurs, V
an amount equal to ΔI
fective series resistance of C
charge or discharge C
signal that forces the regulator to adapt to the current
change and return V
this recovery time V
overshoot or ringing, which would indicate a stability
problem. OPTI-LOOP compensation allows the transient
response to be optimized over a wide range of output
capacitance and ESR values. The availability of the I
not only allows optimization of control loop behavior but
also provides a DC coupled and AC fi ltered closed loop
response test point. The DC step, rise time and settling
at this test point truly refl ects the closed loop response.
Assuming a predominantly second order system, phase
margin and/or damping factor can be estimated using the
percentage of overshoot seen at this pin. The bandwidth
can also be estimated by examining the rise time at the
pin. The I
circuit will provide an adequate starting point for most
applications.
The I
loop compensation. The values can be modifi ed slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the fi nal PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because the various types and values determine the loop
gain and phase. An output current pulse of 20% to 80%
of full-load current having a rise time of 1μs to 10μs will
produce output voltage and I
give a sense of the overall loop stability without break-
ing the feedback loop. Placing a power MOSFET directly
across the output capacitor and driving the gate with an
appropriate signal generator is a practical way to produce
a realistic load step condition. The initial output voltage
TH
series R
TH
external components shown in the Figure 1
C
-C
C
OUT
OUT
fi lter sets the dominant pole-zero
OUT
LOAD
to its steady-state value. During
can be monitored for excessive
generating the feedback error
(ESR), where ESR is the ef-
OUT
TH
pin waveforms that will
. ΔI
LOAD
also begins to
OUT
shifts by
TH
3728fd
pin