ltc4215-1 Linear Technology Corporation, ltc4215-1 Datasheet - Page 19

• Manufacturer Part Number: ltc4215-1
• Description: Hot Swap Controller With Adc And I2c Compatible Monitoring
• Manufacturer: Linear Technology Corporation

APPLICATIONS INFORMATION
once more and latches the data into its control register.
The transmission is ended when the master sends a STOP
condition. If the master continues sending a second data
byte, as in a Write Word command, the second data byte
is acknowledged by the LTC4215-1 but ignored, as shown
in Figure 8.
Read Protocol
The master begins a read operation with a START con-
dition followed by the seven bit slave address and the
R/W bit set to zero, as shown in Figure 9. The addressed
LTC4215-1 acknowledges this and then the master sends
a command byte which indicates which internal register
the master wishes to read. The LTC4215-1 acknowledges
this and then latches the lower three bits of the command
byte into its internal Register Address pointer. The master
then sends a repeated START condition followed by the
same seven bit address with the R/W bit now set to one.
The LTC4215-1 acknowledges and send the contents of
the requested register. The transmission is ended when the
Table 1. LTC4215-1 Device Addressing
*Subset of LTC4215 addresses
DESCRIPTION*
Alert Response
Mass Write
10
11
12
13
14
15
25
8
9
ADDRESS
DEVICE
BE
19
90
92
94
96
98
9A
9C
9E
B2
h
7
1
0
1
1
1
1
1
1
1
1
1
6
0
0
0
0
0
0
0
0
0
0
0
5
1
0
0
0
0
0
0
0
0
0
1
DEVICE ADDRESS
4
1
1
1
1
1
1
1
1
1
1
1
master sends a STOP condition. If the master acknowledges
the transmitted data byte, as in a Read Word command,
Figure 10, the LTC4215-1 repeats the requested register
as the second data byte.
Alert Response Protocol
When any of the fault bits in FAULT register D are set, an
optional bus alert is generated if the appropriate bit in the
ALERT register B is also set. If an alert is enabled, the cor-
responding fault causes the GPIO2 pin to pull low. After
the bus master controller broadcasts the Alert Response
Address, the LTC4215-1 responds with its address on the
SDA line and then release GPIO2 as shown in Figure 11.
The GPIO2 line is also released if the device is addressed
by the bus master. The GPIO2 signal is not pulled low
again until the FAULT register indicates a different fault
has occurred or the original fault is cleared and it occurs
again. Note that this means repeated or continuing faults
do not generate alerts until the associated FAULT register
bit has been cleared.
3
1
1
0
0
0
0
1
1
1
1
0
2
1
0
0
0
1
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
X
X
X
X
X
X
X
X
X
0
0
1
LTC4215-1
ADR1
NC
NC
NC
X
X
H
H
H
L
L
L
ADDRESS PINS
LTC4215-1
ADR0
19
NC
NC
NC
H
H
H
X
X
L
L
L
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