s6b0724 Densitron Corporation, s6b0724 Datasheet - Page 23

• Manufacturer Part Number: s6b0724
• Description: 132 Seg / 65 Com Driver & Controller For Stn Lcd
• Manufacturer: Densitron Corporation

S6B0724
DISPLAY DATA RAM (DDRAM)
The Display Data RAM stores pixel data for the LCD. It is 65-row by 132-column addressable array. Each pixel can
be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines and
the 9th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through
DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines as
shown in figure 6 . The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD
controller operates independently, data can be written into RAM at the same time as data is being displayed without
causing the LCD flicker.
Page Address Circuit
This circuit is for providing a Page Address to DISPLAY-DATA-RAM shown in figure 8. It incorporates 4-bit Page
Address register changed by only the "Set Page" instruction. Page Address 8 (DB3 is "H", but DB2, DB1 and DB0
are "L") is a special RAM area for the icons and display data DB0 is only valid. When Page Address is above 8, it is
impossible to access to on-chip RAM.
Line Address Circuit
This circuit assigns DDRAM a Line A ddress corresponding to the first line (COM0) of the display. Therefore, by
setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the
contents of on-chip RAM as shown in figure 8. It incorporates 6-bit line address register changed by only the initial
display line instruction and 6-bit counter circuit. At the beginning of each LCD frame, the contents of register are
copied to the line counter which is increased by CL signal and generates the Line Address for transferring the
132-bit RAM data to the display data latch circuit. However, display data of icons are not scrolled because the MPU
can not access Line Address of icons.
PRELIMINARY SPEC. VER. 1.1
DB0
DB1
DB2
DB3
DB4
Display Data RAM
0
1
0
1
0
0
0
1
0
0
1
0
1
1
0
Figure 8. RAM-to-LCD Data Transfer
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0
1
0
0
1
132 SEG / 65 COM DRIVER & CONTROLLER FOR STN LCD
COM0
COM1
COM2
COM3
COM4
LCD Display
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