tld4012 Tripath Technology Inc., tld4012 Datasheet
tld4012
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tld4012 Summary of contents
Page 1
... – =19.8dBm LINE OUT EN_AC 1 24 GND 2 23 INP 3 22 INN 4 21 GND (Top View) TLD4012 – JB/Rev. 2.0a/05.02 = 10Vpp NC OUTP NC VDD15 VSS15 NC OUTN NC ...
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... TLD4012 is a low-power, low-distortion ADSL line driver. This driver offers power consumption ranging from 600mW to 650mW, and provides active, or synthetic, output impedance matching to reduce power consumption. This driver supports an impedance synthesis factor of 2.55 (refer to Figure 1 in the “Test/Applications Circuits” section of this document). ...
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... VSS15. 3. The TLD4012 incorporates an exposed die pad on the underside of its package. This acts as a heat sink and must be connected to a copper plane on the printed circuit board for proper heat dissipation. Failure may result in exceeding the maximum junction temperature which could permanently damage the device ...
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... LOPWR = High Gain = 17.8 to 27.8 dB 71: LOAD Gain = 12.8 to 16.8 dB 71: LOAD 500 R = 71: LOAD R = 24k: EXT -100 Gain = 27.8dB, EN_AC = High, 5k: across INN and INP EN_AC = Low LOPWR = High TLD4012 – JB/Rev. 2.0a/05.02 TYP. MAX. UNITS 740 mW 250 mW 130 mW 390 47.0 mA 49 ...
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... MIN. TYP. MAX. UNITS 10 MHz -80 dB -84 dBc -84 -75 -90 dBc -77 -70 -83 dBc -82 -63 -93 dBc -67 -55 200 V/µs 8 nV/—Hz 2.9 pA/—Hz 188 nV/— -0.4 0.4 dB TLD4012 – JB/Rev. 2.0a/05.02 ...
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... Feedback path for synthesized output impedance A logic high forces an immediate reset of the fault latch when RESETB is a logic high. A logic low requires that the RESETB pin be pulsed low to reset the fault latch Exposed pad at underside of device; must be connected to VSS15. Internally connected to the substrate. TLD4012 – JB/Rev. 2.0a/05.02 ...
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... GND OUTP VDD15 20 VSS15 OUTN TLD4012 – JB/Rev. 2.0a/05.02 ...
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... The gain of the TLD4012 is programmed by the digital inputs G3, G2, G1 and G0. The gain given below is the gain from the input to the output of the TLD4012 with R Note that output voltage swing is limited for gains less than 17 ...
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... The TLD4012 can be placed in a lower power disabled mode by holding RESETB to a logic low level. In this mode the power dissipation is only 10 mW, and the line is not terminated so reception of incoming signals is not reliable. In this mode the outputs are high impedance as long as they are not driven externally more than about +/-2 ...
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... Device TLD4012 employs synthesized output impedance with a synthesis factor of 2.55. As with any line driver, using synthesized impedance reduces power consumption, but may compromise receive-signal strength in some applications ...
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... P DISS supplies. The TLD4012 incorporates an exposed die pad on the underside of its package. This acts as a heat sink and should be connected to a copper plane on the printed circuit board for optimum heat dissipation. This copper plane must be connected to VSS15. ...
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... TLD4012 – JB/Rev. 2.0a/05.02 ...
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... Orchard Parkway, San Jose, CA 95131 408.750.3000 - P 408.750.3001 - F For more Sales Information, please visit us @ For more Technical Information, please visit www.tripath.com/cont_s.htm www.tripath.com/data.htm TLD4012 – JB/Rev. 2.0a/05.02 ...