fs6261-01 ETC-unknow, fs6261-01 Datasheet

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fs6261-01

Manufacturer Part Number
fs6261-01
Description
Motherboard Clock Generator
Manufacturer
ETC-unknow
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FS6261-01
Manufacturer:
AMI
Quantity:
20 000
January 2000
1.0
Figure 1: Block Diagram
Intel and Pentium are registered trademarks of Intel Corporation. Spread spectrum modulation is licensed under US Patent No. 5488627, Lexmark International, Inc. American Microsystems, Inc.
reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
SEL_133/100#
CPU_STOP#
PWR_DWN#
PCI_STOP#
Generates clocks required for Intel
desktop and workstation systems, including:
CPU clock cycle – cycle jitter < 150ps p-p
Non-linear spread-spectrum modulation
(-0.5% at 31.5kHz)
Supports test mode and tristate output control
Separate CPU-enable, PCI-enable and power-down
inputs with glitch-free stop clock controls on all clocks
for clock control and power management
SEL_0:1
SS_EN#
XOUT
Features
Four enabled 2.5V 133/100MHz CPU Front Side
Bus (FSB) clocks
Two 2.5V CPU/2 clocks for synchronous memory
Seven enabled 3.3V PCI bus clocks and one
free-running PCI clock
Four enabled 3.3V 66MHz AGP clocks
Three 2.5V 16.67MHz APIC bus clocks
Two 3.3V 14.318MHz REF clocks
One 3.3V 48MHz USB clock
XIN
Oscillator
Crystal
PLL
PLL
delay
delay
delay
÷3 or
÷3 or
÷4
FS6261-01
÷4
÷2
÷6 or
or ÷2
÷1½
÷8
®
i820 based
(2.5V outputs)
VDD_R
REF_0:1
VSS_R
VDD_C2
CPU/2_0:1
VSS_C2
VDD_A
APIC_0:2
VSS_A
VDD_C
CPU_0:3
VSS_C
VDD_66
CK66_0:3
VSS_66
VDD_P
PCI_F
PCI_1:7
VSS_P
VDD_48
CK48
VSS_48
2.0
The FS6261-01 is a CMOS clock generator IC designed
for high-speed motherboard applications. Two different
frequencies can be selected for the CPU clocks via two
SEL pins. Glitch-free stop clock control of the CPU, AGP
(66MHz) and PCI clocks is provided. A low current
power-down mode is available for mobile applications.
Separate clock buffers provide for a 2.5V voltage range
on the CPU_0:3, CPU/2_0:1 and APIC_0:2 clocks.
Figure 2: Pin Configuration
Table 1: CPU/PCI Frequency Selection
SEL_133/100#
0
0
0
0
1
1
1
1
Description
SEL133/100#
VDD_66
VDD_66
VSS_66
VSS_66
CK66_0
CK66_1
CK66_2
CK66_3
SEL_1
VDD_R
VDD_P
VDD_P
VSS_R
VSS_P
VSS_P
VSS_P
REF_0
REF_1
XOUT
PCI_F
PCI_1
PCI_2
PCI_3
PCI_4
PCI_5
PCI_6
PCI_7
XIN
0
0
1
1
0
0
1
1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
56-pin SSOP
SEL_0
0
1
0
1
0
1
0
1
CPU (MHz)
(reserved)
(reserved)
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
tristate
XIN/2
VDD_A
APIC_2
APIC_1
APIC_0
VSS_A
VDD_C2
CPU/2_1
CPU/2_0
VSS_C2
VDD_C
CPU_3
CPU_2
VSS_C
VDD_C
CPU_1
CPU_0
VSS_C
VDD
VSS
PCI_STOP#
CPU_STOP#
PWR_DWN#
SS_EN#
SEL_1
SEL_0
VDD_48
CK48
VSS_48
100
100
133
133
PCI (MHz)
(reserved)
(reserved)
tristate
33.33
33.33
XIN/6
33.33
33.33
1.31.00

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fs6261-01 Summary of contents

Page 1

... Intel and Pentium are registered trademarks of Intel Corporation. Spread spectrum modulation is licensed under US Patent No. 5488627, Lexmark International, Inc. American Microsystems, Inc. reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. 2.0 ® The FS6261- CMOS clock generator IC designed i820 based for high-speed motherboard applications. Two different frequencies can be selected for the CPU clocks via two SEL pins ...

Page 2

Table 2: Pin Descriptions Key Analog Input Analog Output Digital Input Digital Output Power/Ground Active-low pin PIN TYPE NAME 53, 54 APIC_0 CK48 ...

Page 3

January 2000 Table 3: Actual Clock Frequencies Note: Spread spectrum disabled CLOCK APIC_0:2 CPU_0:3 CPU/2_0:1 PCI_1:7, PCI_F CK66_0:3 (1) CK48 (1) 48MHz USB clock is required to be 167ppm off from 48.000MHz to conform to USB requirements. 3.0 Programming Information ...

Page 4

SEL_1, SEL_0 These two input pins can either tristate the output drivers, select the Test Mode frequency, or choose the CPU fre- quencies. Both the SEL_1 and SEL_0 pins have pull-ups that default the CPU output frequency to either ...

Page 5

January 2000 Figure 2: CPU_STOP# Timing CPU_ STOP# PCI_F CPU (133MHz) CPU (100MHz) Figure 3: PCI_STOP# Timing PCI_ STOP# PCI_F PCI_1:7 Figure 4: PWR_DWN# Timing PWR_ DWN# PCI_F PCI_1:7 CPU (133MHz) CPU (100MHz) VCO Crystal Oscillator Shaded regions in the ...

Page 6

Spread Spectrum Modulation To limit peak EMI emissions, high-speed motherboard designs now require the reduction of the peak harmonic energy contained in the system bus frequencies. A re- duction in the peak energy of a specific frequency can be ...

Page 7

January 2000 Compared to the profile limits the modulation slew rate is relatively slow between the limits, allowing the down- stream PLL a chance to reduce the tracking skew. The ability of the downstream PLL to catch up is determined ...

Page 8

Electrical Specifications Table 6: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any ...

Page 9

January 2000 Table 8: DC Electrical Specifications Unless otherwise stated, all power supplies = 3.3V ± 10%, no load on any output, and ambient temperature range T characterization data and are not currently production tested to any specific limits. MIN ...

Page 10

Table 8: DC Electrical Specifications, continued Unless otherwise stated, all power supplies = 3.3V ± 10%, no load on any output, and ambient temperature range T characterization data and are not currently production tested to any specific limits. MIN and ...

Page 11

January 2000 Table 9: AC Timing Specifications Unless otherwise stated, all power supplies = 3.3V ± 10%, no load on any output, and ambient temperature range T characterization data and are not currently production tested to any specific limits. MIN ...

Page 12

Table 9: AC Timing Specifications, continued Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature T are not currently production tested to any specific limits. MIN and MAX characterization data are PARAMETER CPU_0:3 ...

Page 13

January 2000 Table 9: AC Timing Specifications, continued Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature T are not currently production tested to any specific limits. MIN and MAX characterization data are ...

Page 14

Figure 10: DC Measurement Points V = 2. 0.4V OL 3.3 (device interface) A. 3.3V Clock Interface Figure 11: Timing Diagrams Duty Cycle A. 3.3V Clock Interface Table 10: CPU_0:3, CPU/2_0:1, APIC_0:2 ...

Page 15

January 2000 Table 11: REF_0:1, CK48 Clock Outputs High Drive Current (mA) Voltage (V) MIN. TYP. MAX ...

Page 16

Package Information Table 13: 56-pin SSOP (0.300") Package Dimensions DIMENSIONS INCHES MILLIMETERS MIN. MAX. MIN. MAX. A 0.095 0.110 2.41 2.79 A 0.008 0.016 0.203 0.406 1 A 0.088 0.092 2.24 2. 0.008 0.0135 0.203 0.343 C ...

Page 17

... January 2000 8.0 Ordering Information Table 15: Device Ordering Codes DEVICE NUMBER ORDERING CODE 11565-801 FS6261-01 11565-811 9.0 Revision Information DATE PAGE DESCRIPTION 1/31/00 11-13 Updated characterization data Copyright © 1999, 2000 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement ...

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