scan921226hsmx National Semiconductor Corporation, scan921226hsmx Datasheet
scan921226hsmx
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scan921226hsmx Summary of contents
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... This eliminates transmission errors Block Diagrams © 2005 National Semiconductor Corporation due to charged cable conditions. Furthermore, you may put the SCAN921025H output pins into TRI-STATE to achieve a high impedance state. The PLL can lock to frequencies between 20 MHz and 80 MHz ...
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Block Diagrams (Continued) Functional Description The SCAN921025H and SCAN921226H are a 10-bit Serial- izer and Deserializer chipset designed to transmit data over differential backplanes at clock speeds from MHz. The chipset is also capable of driving data ...
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Data Transfer (Continued) high, PWRDN = high, and SYNC1 and SYNC2 are low. When DEN is driven low, the Serializer output pins will enter TRI-STATE. When the Deserializer synchronizes to the Serializer, the LOCK pin is low. The Deserializer locks ...
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Test Modes (Continued) system clocks (At a SCLK of 66Mhz and TCK of 1MHz this allows for 66 TCK cycles). This is not a concern when both devices are on the same scan chain or LSP, however, it can be ...
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Absolute Maximum Ratings Supply Voltage ( LVCMOS/LVTTL Input Voltage LVCMOS/LVTTL Output Voltage Bus LVDS Receiver Input Voltage Bus LVDS Driver Output Voltage Bus LVDS Output Short Circuit Duration Junction Temperature Storage Temperature Lead Temperature (Soldering, 4 seconds) Maximum ...
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Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter DESERIALIZER Bus LVDS DC SPECIFICATIONS (apply to pins RI+ and RI−) VTH Differential Threshold High Voltage VTL Differential Threshold Low Voltage I Input Current IN SERIALIZER ...
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Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t DIN (0-9) Setup to TCLK R DIS C t DIN (0-9) Hold from DIH Figure 7 TCLK ± HIGH to R HZD ...
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Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions t HIGH to TRI-STATE Figure 14 HZR Delay t LOW to TRI-STATE LZR Delay t TRI-STATE to HIGH ZHR Delay t TRI-STATE to LOW ...
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AC Timing Diagrams and Test Circuits FIGURE 2. “Worst Case” Serializer ICC Test Pattern FIGURE 3. “Worst Case” Deserializer ICC Test Pattern FIGURE 4. Serializer Bus LVDS Output Load and Transition Times FIGURE 5. Deserializer CMOS/TTL Output Load and Transition ...
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AC Timing Diagrams and Test Circuits Timing shown for TCLK_R/F = LOW FIGURE 8. Serializer TRI-STATE Test Circuit and Timing www.national.com (Continued) FIGURE 6. Serializer Input Clock Transition Time FIGURE 7. Serializer Setup/Hold Times 10 20120707 20120708 20120709 ...
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AC Timing Diagrams and Test Circuits FIGURE 9. Serializer PLL Lock Time, and PWRDN TRI-STATE Delays (Continued) FIGURE 10. SYNC Timing Delays FIGURE 11. Serializer Delay 11 20120710 20120723 20120711 www.national.com ...
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AC Timing Diagrams and Test Circuits Timing shown for RCLK_R/F = LOW Duty Cycle ( RDC FIGURE 14. Deserializer TRI-STATE Test Circuit and Timing www.national.com (Continued) FIGURE 12. Deserializer Delay FIGURE 13. Deserializer Data Valid Out Times 12 ...
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AC Timing Diagrams and Test Circuits FIGURE 15. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays FIGURE 16. Deserializer PLL Lock Time from SyncPAT (Continued) 13 20120715 20120722 www.national.com ...
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AC Timing Diagrams and Test Circuits + − (DO )–( Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode. www.national.com (Continued) 20120716 FIGURE 17. V Diagram OD 14 ...
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Application Information USING THE SCAN921025H AND SCAN921226H The Serializer and Deserializer chipset is an easy to use transmitter and receiver pair that sends 10 bits of parallel LVTTL data over a serial Bus LVDS link up to 800 Mbps. An ...
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Application Information USING t AND t TO VALIDATE SIGNAL QUALITY DJIT RNM The parameter t is calculated by first measuring how RNM much of the ideal bit the receiver needs to ensure correct sampling. After determining this amount, what remains ...
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Application Information t is the ideal noise margin on the left of the figure negative value to indicate early with respect to ideal. RNMI the ideal noise margin on the right of the above figure, ...
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Pin Diagrams www.national.com SCAN921025HSM - Serializer (Top View) 20120730 SCAN921226HSM - Deserializer (Top View) 20120731 18 ...
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Serializer Pin Descriptions Pin Name I/O DIN I TCLKR/F I DO+ O DO− O DEN I PWRDN I TCLK I SYNC I DVCC I DGND I AVCC I AGND I TDI I TDO O TMS I TCK I TRST I ...
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Deserializer Pin Descriptions Pin Name I/O ROUT O RCLKR/F I RI+ I RI− I PWRDN I LOCK O RCLK O REN I DVCC I DGND I AVCC I AGND I REFCLK I TDI I TDO O TMS I TCK I ...
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Physical Dimensions inches (millimeters) unless otherwise noted Order Number SCAN921025HSM or SCAN921226HSM National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice ...