s908gr16ag4cfj Freescale Semiconductor, Inc, s908gr16ag4cfj Datasheet - Page 241

• Manufacturer Part Number: s908gr16ag4cfj
• Description: M68hc08 Microcontrollers Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Enter monitor mode with pin configuration shown in
RST latches monitor mode. Once monitor mode is latched, the levels on the port pins except PTA0 can
change.
Once out of reset, the MCU waits for the host to send eight security bytes (see
security bytes, the MCU sends a break signal (10 consecutive 0s) to the host, indicating that it is ready to
receive a command.
19.3.1.1 Normal Monitor Mode
If V
of the input clock. If PTB4 is high with V
will be a divide-by-four of the input clock. Holding the PTB4 pin low when entering monitor mode causes
a bypass of a divide-by-two stage at the oscillator only if V
CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input directly generates internal
bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus frequency.
When monitor mode was entered with V
as long as V
This condition states that as long as V
V
then the COP will be disabled. In the latter situation, after V
removed from the IRQ pin in the interest of freeing the IRQ for normal functionality in monitor mode.
19.3.1.2 Forced Monitor Mode
If entering monitor mode without high voltage on IRQ, all port B pin requirements and conditions, including
the PTB4 frequency divisor selection, are not in effect. This is to reduce circuit requirements when
performing in-circuit programming.
An external oscillator of 8 MHz is required for a baud rate of 7200, as the internal bus frequency is
automatically set to the external frequency divided by four.
When the forced monitor mode is entered the COP is always disabled regardless of the state of IRQ or
RST.
19.3.1.3 Monitor Vectors
In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt
than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow
code execution from the internal monitor firmware instead of user code.
Table 19-2
Freescale Semiconductor
TST
TST
is applied to RST after the initial reset to get into monitor mode (when V
is applied to IRQ and PTB4 is low upon monitor mode entry, the bus frequency is a divide-by-two
summarizes the differences between user mode and monitor mode.
TST
If the reset vector is blank and monitor mode is entered, the chip will see an
additional reset cycle after the initial power-on reset (POR). Once the reset
vector has been programmed, the traditional method of applying a voltage,
V
TST
is applied to either IRQ or RST.
, to IRQ must be used to enter monitor mode.
MC68HC908GR16A Data Sheet, Rev. 1.0
TST
TST
TST
is maintained on the IRQ pin after entering monitor mode, or if
applied to IRQ upon monitor mode entry, the bus frequency
on IRQ, the computer operating properly (COP) is disabled
NOTE
Table 19-1
TST
TST
is applied to IRQ. In this event, the
with a power-on reset. The rising edge of
is applied to the RST pin, V
TST
19.3.2
was applied to IRQ),
Monitor Module (MON)
Security). After the
TST
can be
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