ad73411 Analog Devices, Inc., ad73411 Datasheet - Page 22

• Manufacturer Part Number: ad73411
• Description: Low-power Analog Front End With Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

AD73411
The AD73411 can respond to eleven interrupts. There can be
up to six external interrupts (one edge-sensitive, two level-
sensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte DMA
port and the power-down circuitry. There is also a master RESET
signal. The two serial ports provide a complete synchronous
serial interface with optional companding in hardware and a
wide variety of framed or frameless data transmit and receive
modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The AD73411 provides up to 13 general-purpose flag pins. The
data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs and three flags are
always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n pro-
cessor cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
The DSP section incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.
Following is a brief list of the capabilities of the SPORTs. For
additional information on Serial Ports, refer to the ADSP-2100
Family User’s Manual, Third Edition.
• SPORTs are bidirectional and have a separate, double-
• SPORTs can use an external serial clock or generate their
• SPORTs have independent framing for the receive and trans-
• SPORTs support serial data word lengths from 3 to 16 bits
• SPORT receive and transmit sections can generate unique
• SPORTs can receive and transmit an entire circular buffer of
• SPORT0 has a multichannel interface to selectively receive
• SPORT1 can be configured to have two external interrupts
buffered transmit and receive section.
own serial clock internally.
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
and provide optional A-law and µ-law companding according
to CCITT recommendation G.711.
interrupts on completing a data word transfer.
data with only one overhead cycle per data word. An inter-
rupt is generated after a data buffer transfer.
and transmit a 24- or 32-word, time-division multiplexed,
serial bitstream.
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
DSP SECTION PIN DESCRIPTIONS
The AD73411 is available in a 119-ball PBGA package. In order
to maintain maximum functionality and reduce package size and
pin count, some serial port, programmable flag, interrupt, and
external bus pins have dual, multiplexed functionality. The exter-
nal bus pins are configured during RESET only, while serial port
pins are software configurable during program execution. Flag
and interrupt functionality is retained concurrently on multi-
plexed pins. In cases where pin functionality is reconfigurable,
the default state is shown in plain text; alternate functionality is
shown in italics. See Pin Function Descriptions section.
Memory Interface Pins
The AD73411 processor can be used in one of two modes, Full
Memory Mode, which allows BDMA operation with full exter-
nal overlay memory and I/O capability, or Host Mode, which
allows IDMA operation with limited external addressing capa-
bilities. The operating mode is determined by the state of the
Mode C pin during RESET and cannot be changed while the
processor is running. See Full Memory Mode Pins and Host
Mode Pins charts for descriptions.
Full Memory Mode Pins (Mode C = 0)
Pin
Name(s)
A13:0
D23:0
Host Mode Pins (Mode C = 1)
Pin
Name(s)
IAD15:0
A0
D23:8
IWR
IRD
IAL
IS
IACK
NOTE
In Host Mode, external peripheral addresses can be decoded using the A0,
CMS, PMS, DMS, and IOMS signals.
# of
Pins
14
24
# of
Pins
16
1
16
1
1
1
1
1
Input/
Output Function
O
I/O
Input/
Output Function
I/O
O
I/O
I
I
I
I
O
Address Output Pins for Program,
Data, Byte, and I/O Spaces
Data I/O Pins for Program, Data,
Byte, and I/O Spaces (8 MSBs are
also used as Byte Memory
addresses)
IDMA Port Address/Data Bus
Address Pin for External I/O,
Program, Data, or Byte Access
Data I/O Pins for Program, Data
Byte and I/O Spaces
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge