ics843001agt Integrated Device Technology, ics843001agt Datasheet - Page 9

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ics843001agt

Manufacturer Part Number
ics843001agt
Description
Femto Clocks Crystal-to- 3.3v Lvpecl Clock Generator
Manufacturer
Integrated Device Technology
Datasheet
L
Figure 3A shows a schematic example of the ICS843001. An
example of LVEPCL termination is shown in this schematic.
Additional LVPECL termination approaches are shown in the
LVPECL Termination Application Note. In this example, an 18pF
PC B
Figure 3B shows an example of ICS843001 P.C. board layout.
The crystal X1 footprint shown in this example allows installation
of either surface mount HC49S or through-hole HC49 package.
The footprints of other components in this example are listed in
IDT
AYOUT
ICS843001
FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
/ ICS
F
IGURE
OARD
33pF
G
C2
3.3V LVPECL CLOCK GENERATOR
UIDELINE
VCC
3B. ICS843001 PC B
L
AYOUT
R2
10
26.5625MHz
10uF
18pF
E
C3
XAMPLE
X1
C1
27pF
OARD
C4
0.01u
VCCA
L
AYOUT
F
IGURE
1
2
3
4
U1
VCCA
VEE
XTAL_OUT
XTAL_IN
E
3A. ICS843001 S
XAMPLE
ICS843001
FREQ_SEL
VCC
nQ0
9
Q0
parallel resonant crystal is used. The C1 = 27pF and C2 = 33pF
are recommended for frequency accuracy. The C1 and C2 values
may be slightly adjusted for optimizing frequency accuracy.
the Table 6. There should be at least one decoupling capacitor
per power pin. The decoupling capacitors should be located as
close as possible to the power pins. The layout assumes that the
board has clean analog power ground plane.
T
R
R
N
C
C
C
i s
ABLE
8
7
6
5
e
, 1
3
, 4
2
O
CHEMATIC
e z
e f
T
s
C
C
VCC
: E
e r
s
6. F
2
5
n
h
a T
R1
1K
VCC
o
c
w
e
b
e l
OOTPRINT
n
E
n i
XAMPLE
, 6
C5
0.1u
Q
nQ
h t
s i l
s i
s t
a l
Zo = 50 Ohm
Zo = 50 Ohm
c
T
o y
o
ABLE
m
t u
0
0
0
0
S
p
ICS843001AG REV B DECEMBER 6, 2006
4
8
6
6
o
z i
x e
0
0
0
0
n
e
2
5
3
3
82.5
e
a
t n
m
R3
133
R4
p
. e l
VCC
R5
133
R6
82.5
+
-

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