ics84330c Integrated Device Technology, ics84330c Datasheet - Page 12

• Manufacturer Part Number: ics84330c
• Description: 700mhz, Low Jitter, Crystal-to-3.3v Differential Lvpecl Frequency Synthesizer
• Manufacturer: Integrated Device Technology

The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
Power and Grounding
Place the decoupling capacitors C3 and C4, as close as possible
to the power pins. If space allows, placement of the decoupling
capacitor on the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power and
ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed as
close to the V
Clock Traces and Termination
Poor signal integrity can degrade the system performance or cause
system failure. In synchronous high-speed digital systems, the
clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
Figure 6B. ICS84330C PCB Board Layout for ICS84330C
IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER
ICS84330C
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
U1
CCA
C1
C4
pin as possible.
PIN 2
PIN 1
50 Ohm
Traces
C3
X1
C11
R7
C16
VCCA
C2
GND
Signals
Traces
VCC
VCCA
VIA
12
Crystal
The crystal X1 should be located as close as possible to the pins
4 (XTAL1) and 5 (XTAL2). The trace length between the X1 and U1
should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
• The differential 50Ω output traces should have the same
length.
• Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
• Keep the clock traces on the same layer. Whenever
possible, avoid placing vias on the clock traces. Placement of
vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace widths
between the differential clock trace and the other signal trace.
• Make sure no other signal traces are routed between the
clock trace pair.
• The matching termination resistors should be located as
close to the receiver input pins as possible.
ICS84330CV REV. C JANUARY 28, 2009