ics8745b Integrated Device Technology, ics8745b Datasheet - Page 14

• Manufacturer Part Number: ics8745b
• Description: 1 5 Differential-to-lvds Zero Delay Clock Generator
• Manufacturer: Integrated Device Technology

The following component footprints are used in this layout
example.
All the resistors and capacitors are size 0603.
Power and Grounding
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on the
component side is preferred. This can reduce unwanted
inductance between the decoupling capacitor and the power pin
caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power and
ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed as
close to the V
Clock Traces and Termination
Poor signal integrity can degrade the system performance or cause
system failure. In synchronous high-speed digital systems, the
clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
Figure 5B. PCB Board Layout for ICS8745B
IDT™ / ICS™ LVDS ZERO DELAY CLOCK GENERATOR
ICS8745B
1:5 DIFFERENTIAL-TO-LVDS ZERO DELAY CLOCK GENERATOR
U1
Pin 1
C1
C6
DDA
R7
pin as possible.
C16
C11
C5
C2
C4
14
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
• The differential 50Ω output traces should have the same
• Avoid sharp angles on the clock trace. Sharp angle turns
• Keep the clock traces on the same layer. Whenever
• To prevent cross talk, avoid routing other signal traces in
• Make sure no other signal traces are routed between the
• The matching termination resistors should be located as
length.
cause the characteristic impedance to change on the
transmission lines.
possible, avoid placing vias on the clock traces.
Placement of vias on the traces can affect the trace
characteristic impedance and hence degrade signal
integrity.
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
clock trace pair.
close to the receiver input pins as possible.
GND
50 Ohm
Traces
VDDO
VDD
VDDA
VIA
ICS8745BYREV. C OCTOBER 27, 2008