ics8308agit Integrated Device Technology, ics8308agit Datasheet - Page 10

• Manufacturer Part Number: ics8308agit
• Description: Lvcmos/differential-input Lvcmos-output 1 8 350-mhz Clock Buffer
• Manufacturer: Integrated Device Technology

Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
IDT
W
R
I
CLK I
For applications not requiring the use of the test clock, it can be
left floating. Though not required, but for additional protection, a
1k
CLK/nCLK I
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1k
ground.
LVCMOS C
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1k
NPUTS
ECOMMENDATIONS FOR
ICS8308I
LOW SKEW, 1-TO-8 DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
IRING THE
™
/ ICS
resistor can be tied from the CLK input to ground.
NPUT
:
™
LVCMOS FANOUT BUFFER
ONTROL
NPUTS
D
IFFERENTIAL
resistor can be used.
P
INS
U
NUSED
I
NPUT TO
resistor can be tied from CLK to
F
IGURE
I
NPUT AND
Single Ended Clock Input
A
CCEPT
1. S
A
PPLICATION
INGLE
O
S
INGLE
UTPUT
E
NDED
C1
0.1u
DD
V_REF
/2 is
E
P
S
NDED
INS
IGNAL
10
I
L
NFORMATION
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
and R2/R1 = 0.609.
O
LVCMOS O
All unused LVCMOS output can be left floating. There should be
no trace attached.
D
EVELS
1K
RIVING
UTPUTS
R1
1K
R2
VDD
D
CLK
nCLK
:
IFFERENTIAL
UTPUTS
I
NPUT
ICS8308AGI REV. B OCTOBER 16, 2007
DD
= 3.3V, V_REF should be 1.25V