ics86953i-147 Integrated Device Technology, ics86953i-147 Datasheet - Page 9

• Manufacturer Part Number: ics86953i-147
• Description: Low Skew, 1-to-9 Ics86953i-147 Differential-to-lvcmos / Lvttl Zero Delay Buffer
• Manufacturer: Integrated Device Technology

ICS86953I-147
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on the
component side is preferred. This can reduce unwanted inductance
between the decoupling capacitor and the power pin caused by
the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power and
ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed as
close to the V
C
Poor signal integrity can degrade the system performance or cause
system failure. In synchronous high-speed digital systems, the clock
signal is less tolerant to poor signal integrity than other signals. Any
ringing on the rising or falling edge or excessive ring back can
cause system failure. The shape of the trace and the trace delay
ICS86953BYI-147 REVISION B FEBRUARY 26, 2010
OWER AND
LOCK
T
RACES AND
DDA
G
ROUNDING
pin as possible.
T
ERMINATION
C16
C11
R7
F
VCCA
IGURE
Pin 1
U1
4B. PCB B
C2
OARD
R2
50 Ohm
Trace
L
9
AYOUT
C1
LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER
might be restricted by the available space on the board and the
component location. While routing the traces, the clock signal traces
should be routed first and should be locked prior to routing other
signal traces.
• The 50Ω output traces should have same length.
• Avoid sharp angles on the clock trace. Sharp angle turns
• Keep the clock traces on the same layer. Whenever pos-
• To prevent cross talk, avoid routing other signal traces in
• Make sure no other signal traces are routed between the
• The series termination resistors should be located as
cause the characteristic impedance to change on
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
clock trace pair.
close to the driver pins as possible.
F
R1
C3
OR
50 Ohm
Trace
the transmission lines.
ICS86953I-147
C5
C4
©2010 Integrated Device Technology, Inc.
Other
signals
GND
VDD
VIA