ics9248-90 ETC-unknow, ics9248-90 Datasheet
ics9248-90
Related parts for ics9248-90
ics9248-90 Summary of contents
Page 1
... Circuit Systems, Inc. Frequency Generator & Integrated Buffers for PENTIUM/Pro General Description The ICS9248-90 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Cyrix. Eight different reference frequency multiplying factors are externally selectable with smooth frequency transitions. ...
Page 2
... ICS9248-90 Pin Descriptions ...
Page 3
... ICS9248- ...
Page 4
... ICS9248-90 Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = ...
Page 5
... ICS9248-90 ...
Page 6
... ICS9248-90 Byte 4: Reserved Active/Inactive Register (1 = enable disable ...
Page 7
... target Freq 2.5 V +/-5% (unless otherwise stated) DDL CONDITIONS pF; Select @ 66.8 MHz pF; Select @ 100 MHz pF; Select @ 124 MHz pF; Select @ 133 MHz 1 1. ICS9248-90 +0 MIN TYP MAX -0.3 0 2.0 -200 -100 87 170 ...
Page 8
... ICS9248-90 Electrical Characteristics - CPUCLK 70º 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH2B Output Low Voltage V OL2B Output High Current I OH2B Output Low Current I OL2B 1 Rise Time t r2B 1 Fall Time t f2B 1 Duty Cycle d t2B 1 Skew t sk2B 1 Jitter, One Sigma ...
Page 9
... DDL L CONDITIONS ICS9248-90 MIN TYP MAX UNITS 2.4 3.1 V 0.17 0.4 V -60 - 1.87 2.6 ns 1.5 2 124 500 ps 70 150 ps -500 160 500 ps 130 400 ...
Page 10
... ICS9248-90 Electrical Characteristics - REF1 70º 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH5 Output Low Voltage V OL5 Output High Current I OH5 Output Low Current I OL5 1 Rise Time Fall Time Duty Cycle Jitter, One Sigma Jitter, Absolute ...
Page 11
... ACK ACK ACK ACK ACK ACK 2 C component. It can read back the data stored in the latches for 2 C interface, the protocol is set to use only "Block-Writes" from the controller. The ICS9248- programming. How to Read: ICS (Slave/Receiver) Start Bit Address D3 (H) ACK ...
Page 12
... ICS9248-90 Shared Pin Operation - Input/Output Pins Programming Header Via to Gnd Device Pad Via to VDD 2K 8.2K Clock trace to load Series Term. Res. Fig. 1 ...
Page 13
... CPU_STOP asychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-90. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...
Page 14
... ICS9248-90 PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS9248-90 used to turn off the PCICLK (0:4) clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-90 internally. The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP# high pulse least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse width guaranteed ...
Page 15
... Routed Power = Ground Connection Key (component side copper) = Ground Plane Connection = Power Route Connection = Solder Pads = Clock Load ICS9248-90 Ferrite C2 Bead 22µF/20V Tantalum VDD 2.5V Power Route Clock Load ...
Page 16
... ICS9248-90 Ordering Information ICS9248yF-90-T Example: ICS XXXX PPP - T Designation for tape and reel packaging Pattern Number ( digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists digit numbers) ...