ics9fg1901 Integrated Device Technology, ics9fg1901 Datasheet - Page 8

• Manufacturer Part Number: ics9fg1901
• Description: Frequency Generator For P4? ? ? ? ? Cpu, Pci Express? ? ? ? ? & Fully Buffered Dimm Clocks
• Manufacturer: Integrated Device Technology

0962E—01/02/07
NOTES:
1. Measured at 3 db down or half power point.
2. Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
3. Post processed evaluation through Intel supplied Matlab scripts.
4. Refer to FB-DIMM Specification: “High Speed Differential Point-to-Point Link at 1.5 V” for updates to this specification.
5. PCIe* Gen2 filter characteristics are subject to final ratification by PC ISIG. Please check the PCI* SIG for the latest specification. Tested with DBxx00G driven by low phase
noise signal generator such as an Agilent 8133A.
6. These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be extrapolated to this BER target.
7.
8. Guaranteed by design and characterization, not 100% tested in production.
PLL Bandwidth and Peaking
Output phase jitter impact – PCIe*
Output phase jitter impact – FBD
z
= 0.54 is implying a jitter peaking of 3 dB.
PLL Jitter Peaking
PLL Jitter Peaking
PLL Bandwidth
PLL Bandwidth
Integrated
Circuit
Systems, Inc.
Parameter
Gen1
j
j
pll
peak-hibw
peak-lobw
pll
θ
θ
PCIe1
LOBW
FBD
HIBW
(including PLL BW 1.5-22 MHz, z = 0.54,
(including PLL BW 11- 33 Mz, z = 0.54,
Td=10 ns, Ftrk=1.5 MHz )
Td=5 ns, Ftrk=0.2 MHz)
(HIGH_BW# = 0)
(HIGH_BW# = 1)
(HIGH_BW# = 0)
(HIGH_BW# = 1)
Conditions
8
Min
0.7
0
0
2
0
0
Typical
1.28
2.3
77
1
1
Max
108
2.5
1.4
2
4
3
ICS9FG1901
ps RMS 3,4,7,8
Units
MHz
MHz
dB
dB
ps
3,6,7,8
Notes
2,8
2,8
1,8
1,8