ics97ulp877b Integrated Device Technology, ics97ulp877b Datasheet - Page 7

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ics97ulp877b

Manufacturer Part Number
ics97ulp877b
Description
1.8v Low-power Wide-range Frequency Clock Driver
Manufacturer
Integrated Device Technology
Datasheet

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Notes:
1.
2.
0981C—04/05/05
T
Output enable time
Output disable time
Period jitter
Half-period jitter
Input slew rate
Output clock slew rate
Cycle-to-cycle period jitter
Dynamic Phase Offset
Static Phase Offset
t
t
SSC modulation frequency
SSC clock input frequency
deviation
PLL Loop bandwidth (-3 dB
from unity gain)
Switching Characteristics
(Ø)dyn +
jit (per) +
A
= 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
Output to Output Skew
Switching characteristics guaranteed for application frequency range.
Static phase offset shifted by design.
t
t
PARAMETER
skew(o)
(Ø)dyn +
t
skew(o)
1
SYMBOL
t
t
SLr1(o)
t
t
SLr1(i)
t
t
jit(hper)
jit (per)
(Ø)dyn
t
jit(cc+)
jit(cc-)
SPO
skew
t
t
dis
en
(su)
t (h)
2
OE to any output
OE to any output
Input Clock
Output Enable (OE), (OS)
CONDITION
7
160 to 410
160 to 270
271 to 410
160 to 270
271 to 410
160 to 410
160 to 270
271 to 410
271 to 410
160 to 270
271 to 410
(MHz)
30.00
0.00
MIN
-40
-30
-60
-50
0.5
1.5
-50
-20
-50
2.0
1
0
0
ICS97ULP877B
TYP
4.73
5.82
2.5
2.5
0
-0.50
MAX
-40
40
30
60
50
40
50
20
50
80
60
40
30
33
8
8
4
3
UNITS
MHz
v/ns
v/ns
v/ns
kHz
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
%

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