ics1523 Integrated Device Technology, ics1523 Datasheet - Page 14

• Manufacturer Part Number: ics1523
• Description: Video Clock Synthesizer With I?c Programmable Delay
• Manufacturer: Integrated Device Technology

MDS ICS1523 Z
Section 12 Timing Diagrams
Using the DPA above 160 MHz is not recommended. Set DPA_OS = 0 for speeds in excess of 160 MHz to bypass
the DPA. The DPA Resolution Select register (0x5:0~1) is double-buffered. Working registers are loaded only after
a DPA Software reset (0x8=xA)
HSYNC
DPA Offset when
DPA_OS [5-0] = 0
DPA Offset when
DPA_OS [5-0] = 1
DPA Offset when
DPA_OS [5-0] = 2
DPA Offset when
DPA_OS [5-0] = Max
Figure 12-1 DPA Operation
Table 12-1 DPA Offset Ranges
.
.
.
Register 5
1~0
Integrated Device Technology, Inc.
00
01
11
DPA Offset = CLK Period * (# of DPA Elements Selected [0x4:4~0]
Total # of DPA
Elements
(# of DPA Elements Available)[0x5:1-0]
Fixed delay − See
1 unit of DPA delay
16
32
64
2 units of DPA delay
Maximum units of DPA delay
One full speed clock period
14
Selected #
Figure 12-2
Maximum
Tech Support: www.idt.com/go/clockhelp
Elements
0x4:5-0
of DPA
Video Clock Synthesizer with I
0F
1F
3F
and
Figure 12-3
DPA Clock Range in MHz
Min
48
24
12
1 unit of DPA delay
2
C Programmable Delay
Max
160
80
40
Revision 052407
ICS1523