mpc96877 Integrated Device Technology, mpc96877 Datasheet - Page 7

• Manufacturer Part Number: mpc96877
• Description: 1.8 V Pll 1 10 Differential Sdram Clock Driver
• Manufacturer: Integrated Device Technology

IDT™ 1.8 V PLL 1:10 Differential SDRAM Clock Driver
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC96877
1.8 V PLL 1:10 Differential SDRAM Clock Driver
Table 7. Switching Characteristics over Recommended Free-Air Operating Temperature Range Unless Otherwise Noted
(see Notes)
NOTES:
FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA
OE to any Y/Y
OE to any Y/Y
Cycle-to-Cycle period jitter
Static phase offset
Dynamic phase offset
Output clock skew
Period Jitter
Half -period jitter
Output Enable
Input clock slew rate, measured single ended
Output clock slew rate, measured single ended
Output differential-pair cross voltage
SSC modulation frequency
SSC clock input frequency deviation
PLL Loop bandwidth (–3dB from unity gain)
1. There are two different terminations that are used with the following tests. The loadboard in
2. Static Phase offset does not include Jitter.
3. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other.
4. The Output Slew Rate is determined form the IBIS model into the load shown in
5. To eliminate the impact of input slew rates on static phase offset, the input slew rates of Reference Clock Input CK, CK and Feedback Clock
the input and output differential-pair cross voltage only. The loadboard in
For consistency, equal length cables must be used.
Input FBIN, FBIN are recommended to be nearly equal. The 2.5 V/ns slew rates are shown as a recommended target. Compliance with these
Nom values is not mandatory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered DDR2
DIMM application.
Description
Parameter
tjit(hper)
tjit(cc+)
tjit(cc–)
t(ϕ)dyn
tjit(per)
tsk(o)
slr(o)
slr(i)
V
tdis
t(ϕ)
ten
OX
see
see
see
and
and
see
see
see
see
see
see
see
see
Diagram
7
Figure 11
Figure 11
Figure 10
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 3
Figure 3
Figure 2
Figure 9
Figure 9
Figure 3. Output Load Test Circuit 1
Figure 4. Output Load Test Circuit
(V
DDQ
Min
–50
–50
–40
–75
0.5
1.5
0.0
2.0
30
/2) – 0.1
0
0
1
Figure 2. IBIS Model Output Load
AV
DD,
V
DDQ
Nom
= 1.8 V ± 0.1 V
2.5
2.5
is used to measure all other tests.
2. It is measured single ended.
(V
DDQ
Max
–0.5
–40
40
50
50
40
40
75
33
/2) + 0.1
8
8
4
3
is used to measure
MPC96877
NETCOM
Unit
V/ns
V/ns
MHz
kHz
ns
ns
ps
ps
ps
ps
ps
ps
ps
MPC96877
V
553