mpc93h52 Integrated Device Technology, mpc93h52 Datasheet - Page 9

• Manufacturer Part Number: mpc93h52
• Description: 3.3v/ 2.5v Lvcmos 1 11 Clock Generator
• Manufacturer: Integrated Device Technology

IDT™ 3.3 V 1:11 LVCMOS Zero Delay Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC93H52
3.3 V 1:11 LVCMOS Zero Delay Clock Generator
Advanced Clock Drivers Devices
Freescale Semiconductor
is specified. I/O jitter numbers for other confidence factors
(CF) can be derived from
Table 9. Confidence Factor CF
layout and can be used to fine-tune the effective delay
through each device. In the following example calculation, an
I/O jitter confidence factor of 99.7% (± 3σ) is assumed,
resulting in a worst case timing uncertainty from input to any
output of –445 ps to 395 ps relative to CCLK:
t
t
Driving Transmission Lines
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20 Ω, the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines, the reader is referred to Freescale application note
AN1091. In most high performance clock networks,
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme, either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50 Ω resistance to V
thus, only a single terminated line can be driven by each
output of the MPC93H52 clock driver. For the series
terminated case, however, there is no DC current draw, thus
the outputs can drive multiple series terminated lines.
Figure 9
terminated line versus two series terminated lines in parallel.
When taken to its extreme, the fanout of the MPC93H52
clock driver is effectively doubled due to its capability to drive
multiple lines.
SK(PP)
SK(PP)
± 1σ
± 2σ
± 3σ
± 4σ
± 5σ
± 6σ
CF
Due to the statistical nature of I/O jitter a RMS value (1 σ)
The feedback trace delay is determined by the board
The MPC93H52 clock driver was designed to drive high-
This technique draws a fairly high level of DC current and,
= [–200ps...150ps] + [–200ps...200ps] +
= [–445ps...395ps] + t
illustrates an output driving a single series
Probability of Clock Edge within the Distribution
[(15ps
•
–3)...(15ps
CC
÷2.
Table
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
•
PD, LINE(FB)
9.
3)] + t
PD, LINE(FB)
9
simulation results of an output driving a single line versus two
lines. In both cases, the drive capability of the MPC93H51
output buffer is more than sufficient to drive 50 Ω
transmission lines on the incident edge. Note from the delay
measurements in the simulations, a delta of only 43 ps exists
between the two differently loaded outputs. This suggests
that the dual line driving need not be used exclusively to
maintain the tight output-to-output skew of the MPC93H51.
The output waveform in
step in the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36 Ω series resistor, plus the output
impedance, does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
unity reflection coefficient, to 2.7 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance, the line
impedance is perfectly matched.
IN
IN
The waveform plots in
At the load end, the voltage will double, due to the near
Since this step is well above the threshold region, it will not
Figure 9. Single versus Dual Transmission Lines
MPC93H52
MPC93H52
OUTPUT
OUTPUT
BUFFER
BUFFER
10Ω
10Ω
Figure 11
V
Z
R
R
V
L
0
L
S
0
= V
= 50 Ω || 50 Ω
= 40 Ω || 40 Ω
= 10 Ω
= 3.0 (25 ÷ (20 + 10 + 25)
= 1.36 V
S
should be used. In this case, the series
(Z
Figure 10
R
R
R
0
Figure 10
S
S
S
÷ (R
= 40Ω
=40Ω
=40Ω
S
+ R
and
and
Z
Z
Z
0
O
O
O
+ Z
= 50Ω
= 50Ω
= 50Ω
Figure 11
Figure 11
0
))
MPC93H52
shows a
show the
OutA
OutB0
OutB1
NETCOM
MPC93H52
9