mpc9892 ETC-unknow, mpc9892 Datasheet - Page 2

• Manufacturer Part Number: mpc9892
• Description: Intelligent Dynamic Clock Switch
• Manufacturer: ETC-unknow

MPC9892
PIN DESCRIPTIONS
Manual_Override
MOTOROLA
CLK0, CLK0
CLK1, CLK1
Ext_FB, Ext_FB
Qa0:1, Qa0:1
Qb0:2, Qb0:2
Inp0bad
Inp1bad
Clk_Selected
Alarm_Reset
Sel_Clk
PLL_En
MR
VCCA
VCC
GNDA
GND
Pin Name
LVCMOS Output
LVCMOS Output
LVCMOS Output
LVPECL Output
LVPECL Output
LVCMOS Input
LVCMOS Input
LVCMOS Input
LVCMOS Input
LVCMOS Input
LVPECL Input
LVPECL Input
LVPECL Input
Power Supply
Power Supply
Power Supply
Power Supply
Man_Override
I/O
VCC_PLL
PLL_En
VCC
Qa1
Qa1
Qa0
Qa0
Differential PLL clock reference (CLK0 pulldown, CLK0 pullup)
Differential PLL clock reference (CLK1 pulldown, CLK1 pullup)
Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup)
Differential 1x output pairs
Differential 4x output pairs
Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output
is active HIGH and will remain HIGH until the alarm reset is asserted
Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output
is active HIGH and will remain HIGH until the alarm reset is asserted
‘0’ if clock 0 is selected, ‘1’ if clock 1 is selected
‘0’ will reset the input bad flags and align Clk_Selected with Sel_Clk. The input is “one–shotted”
(50k pullup)
‘0’ selects CLK0, ‘1’ selects CLK1 (50k pulldown)
‘1’ disables internal clock switch circuitry (50k pulldown)
‘0’ bypasses selected input reference around the phase–locked loop (50k pullup)
‘0’ resets the internal dividers forcing Q outputs LOW. Asynchronous to the clock (50k pullup)
PLL power supply
Digital power supply
PLL ground
Digital ground
25
26
27
28
29
30
31
32
Figure 2. 32–Lead Pinout (Top View)
24
1
23
2
22
3
MPC9892
21
4
2
20
5
19
6
18
7
Pin Definition
17
8
16
15
14
13
12
10
11
9
VCC
Inp0bad
Inp1bad
Clk_Selected
GND
Ext_FB
Ext_FB
GND
TIMING SOLUTIONS