mpc9774 Integrated Device Technology, mpc9774 Datasheet
mpc9774
Available stocks
Related parts for mpc9774
mpc9774 Summary of contents
Page 1
... LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines, each of the MPC9774 outputs can drive one or two traces giving the devices an effective fanout of 1:12. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP package. ...
Page 2
... Ref 1 VCO ÷4 1 PLL ÷4, ÷6, ÷8, ÷12 200-500 MHz FB Figure 1. MPC9774 Logic Diagram MPC9774 Figure 2. MPC9774 52–Lead Package Pinout (Top View) 2 For More Information On This Product, Go to: www.freescale.com 2 Bank A QA0 QA1 CLK ÷2, ÷4 QA2 STOP ÷2, ÷4 QA3 ÷ ...
Page 3
... During reset/output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The MPC9774 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLKx). The device is reset by the internal power– ...
Page 4
... I Maximum Quiescent Supply Current CCQ a. The MPC9774 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage Inputs have pull-down or pull-up resistors affecting the input current. IDT™ 3.3V 1:14 LVCMOS PLL Clock Generator ...
Page 5
... LOCK a AC characteristics apply for parallel output termination of 50Ω bypass mode, the MPC9774 divides the input reference clock. c The input reference frequency must match the VCO lock range divided by the total feedback divider ratio (FB Calculation of reference duty cycle limits: DC the input duty cycle range is 12.5% < ...
Page 6
... MPC9774 3.3V 1:14 LVCMOS PLL Clock Generator MPC9774 MPC9774 Configurations Configuring the MPC9774 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: ⋅ ÷ ÷ where f is the reference frequency of the selected input REF clock source (CCLKO or CCLK1 the PLL feedback divider and output divider ...
Page 7
... CMOS fanout buffers. The external feedback of the MPC9774 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated) ...
Page 8
... Termination Waveforms” show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9774 output buffer is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs ...
Page 9
... The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9774. Figure 11 illustrates a typical power supply filter scheme. The MPC9774 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range ...
Page 10
... Figure 14. Propagation delay (t SK( 100 For More Information On This Product, Go to: www.freescale.com 10 NETCOM B B ∅ , static phase (∅) offset) test reference mean JIT( ∅ Figure 16. I/O Jitter ÷ f JIT(PER Figure 18. Period Jitter TIMING SOLUTIONS MPC9774 ...
Page 11
... For More Information On This Product, Go to: www.freescale.com 11 NETCOM MPC9774 –X– X= VIEW Y MILLIMETERS INCHES DIM MIN MAX MIN MAX θ θ θ θ3 MPC9774 MOTOROLA ...
Page 12
... MPC92459 MPC9774 PART NUMBERS 900 MHz Low Voltage LVDS Clock Synthesizer 3.3V 1:14 LVCMOS PLL Clock Generator INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. ...