mpc97h73 Integrated Device Technology, mpc97h73 Datasheet
mpc97h73
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mpc97h73 Summary of contents
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... The MPC97H73 also supports the 180° phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of system baseline timing signals ...
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... MPC97H73 3.3V 1:12 LVCMOS PLL Clock Generator MPC97H73 Figure 2. MPC97H73 52–Lead Package Pinout (Top View) IDT™ 3.3V 1:12 LVCMOS PLL Clock Generator MOTOROLA Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor, Inc. Ω 0 ÷ ÷ ÷ ÷ ...
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... Selects VCO÷2. The VCO frequency is scaled by a factor of 2 (low VCO frequency range). PLL_EN 1 Test mode with the PLL bypassed. The reference clock is substituted for the internal VCO output. MPC97H73 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. INV_CLK 1 ...
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... VCO÷8 FSEL_FB0 QFB 0 VCO÷8 1 VCO÷12 0 VCO÷16 1 VCO÷20 0 VCO÷16 1 VCO÷24 0 VCO÷32 1 VCO÷40 0 VCO÷4 1 VCO÷6 0 VCO÷8 1 VCO÷10 0 VCO÷8 1 VCO÷12 0 VCO÷16 1 VCO÷20 TIMING SOLUTIONS NETCOM MPC97H73 ...
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... CMR and the input swing lies within the V b. The MPC97H73 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage Inputs have pull–down resistors affecting the input current. ...
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... MHz 1000 mV LVPECL V -0.9 V LVPECL CC ns 1.0 ns 0.8 to 2.0V PLL locked ° +3 ° +4 +166 ps 100 ps 100 ps 100 ps 250 ps T÷2 (T÷2) +200 ps 1.0 ns 0.55 to 2.4V 8.0 ns 8.0 ns 150 200 ps 150 (VCO=400 MHz TIMING SOLUTIONS NETCOM MPC97H73 ...
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... Normal AC operation is obtained when the crosspoint is within the V CMR and the input swing lies within the V d Calculation of reference duty cycle limits The MPC97H73 will operate with input rise/fall times up to 3.0 ns, but the A.C. characteristics, specifically t only be guaranteed are within the specified range CCLKx or PCLK to FB_IN ...
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... MPC97H73 3.3V 1:12 LVCMOS PLL Clock Generator MPC97H73 MPC97H73 Configurations Configuring the MPC97H73 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: ⋅ ÷ ÷ where f is the reference frequency of the selected input REF clock source (CCLKO, CCLK1 or PCLK the PLL feedback divider and output divider ...
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... NRZ disable/enable bits. The period of each STOP_DATA bit equals the period of the free–running STOP_CLK signal. The STOP_DATA serial transmission should be timed so the MPC97H73 can sample each STOP_DATA bit with the rising edge of the free–running STOP_CLK signal. (see Figure 5. ) Figure 5 ...
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... QSYNC. In configurations with the output frequency relationships are not integer multiples of each other QSYNC provides a signal for system synchronization purposes. The MPC97H73 monitors the relationship between the A bank and the B bank of outputs. The QSYNC output is asserted (logic low) one period in duration and one period prior to the ÷ ...
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... CMOS fanout buffers. The external feedback option of the ) CC MPC97H73 clock driver allows for its use as a zero delay ) of the device. The buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated) ...
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... V This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC97H73 clock driver. For the series terminated case however there current draw, thus 12 For More Information On This Product, Go to: www ...
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... Figure 12. “Single versus Dual Transmission Lines” illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC97H73 clock driver is effectively doubled due to its capability to drive multiple lines. Ω Ω Ω ...
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... IDT™ 3.3V 1:12 LVCMOS PLL Clock Generator MOTOROLA Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor, Inc. Ω Ω Figure 15. CCLK MPC97H73 AC test reference Ω Ω Figure 16. PCLK MPC97H73 AC test reference 14 For More Information On This Product, Go to: www.freescale.com 14 NETCOM Ω Ω Ω ...
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... Figure 18. Propagation delay (t SK( 100 JIT(CC) N N+1 15 For More Information On This Product, Go to: www.freescale.com 15 NETCOM MPC97H73 B B ∅ , static phase (∅) offset) test reference mean JIT(∅ Figure 20. I/O Jitter JIT(PER Figure 22. Period Jitter MPC97H73 MOTOROLA ...
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... For More Information On This Product, Go to: www.freescale.com 16 NETCOM –X– X= VIEW Y MILLIMETERS INCHES DIM MIN MAX MIN MAX θ θ θ θ3 MPC97H73 TIMING SOLUTIONS ...
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... MPC92459 MPC97H73 PART NUMBERS 900 MHz Low Voltage LVDS Clock Synthesizer 3.3V 1:12 LVCMOS PLL Clock Generator INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales 800-345-7015 408-284-8200 Fax: 408-284-2775 Corporate Headquarters Integrated Device Technology, Inc. ...