mpc97h74 Integrated Device Technology, mpc97h74 Datasheet
mpc97h74
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mpc97h74 Summary of contents
Page 1
... LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines, each of the MPC97H74 outputs can drive one or two traces giving the devices an effective fanout of 1:28. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP package. ...
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... GND 48 QC1 QC0 51 GND Figure 2. MPC97H74 52-Lead Package Pinout (Top View) 2 Bank A QA0 QA1 CLK ÷ 2, ÷ 4 QA2 Stop ÷ 2, ÷ 4 QA3 ÷ 4, ÷ 6 QA4 Bank B QB0 QB1 CLK QB2 Stop QB3 ...
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... Outputs disabled (high-impedance state) and reset of the device. During reset/output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The MPC97H74 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLKx) ...
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... CC_PLL I Maximum Quiescent Supply Current CCQ 1. The MPC97H74 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage Inputs have pull-down or pull-up resistors affecting the input current. MPC97H74 IDT™ 3.3 V 1:14 LVCMOS PLL Clock Generator ...
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... Output Frequency Range MAX 1. The input reference frequency must match the VCO frequency lock range divided by the total feedback divider ratio (FB): f × VCO_SEL bypass mode, the MPC97H74 divides the input reference clock. Table 9. AC CHARACTERISTICS (V Symbol Characteristics t Input Reference Pulse Width ...
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... MPC97H74 3.3 V 1:14 LVCMOS PLL Clock Generator MPC97H74 Configurations Configuring the MPC97H74 amounts to properly configuring the internal dividers to produce the desired output frequencies. The output frequency can be represented by this formula: × M ÷ OUT REF f ÷VCO_SEL REF PLL ÷ M where f is the reference frequency of the selected input ...
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... CMOS fanout buffers. The external feedback of the MPC97H74 clock driver allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge resulting a near zero delay through the device (the propagation delay through the device is virtually eliminated) ...
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... In both cases the drive capability of the MPC97H74 output buffer is more than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs ...
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... From the data sheet the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above CC_PLL the bandwidth of the PLL. Although the MPC97H74 has several design features to minimize the susceptibility to shown in Figure 11. power supply noise (isolated power and grounds and fully ...
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... Offset) Test Reference – t mean| JIT(ý for a controlled edge with respect Figure 16. I/O Jitter – (1 ÷ JIT(PER Figure 18. Period Jitter 2.4 0.55 R Advanced Clock Driver Devices Freescale Semiconductor NETCOM ÷ 2 ÷ MPC97H74 ...
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... BSC 0.472 BSC S1 6.00 BSC 0.236 BSC U 0.09 0.16 0.004 0.006 V 12.00 BSC 0.472 BSC V1 6.00 BSC 0.236 BSC W 0.20 REF 0.008 REF Z 1.00 REF 0.039 REF θ 0˚ 7˚ 0˚ 7˚ θ1 --- --- 0˚ 0˚ θ2 12˚ REF 12˚ REF θ3 12˚ REF 12˚ REF MPC97H74 NETCOM MPC97H74 11 ...
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... MC100EP111 MC88LV926 MPC97H74 MPC92459 PART NUMBERS 3.3 V 1:14 LVCMOS PLL Clock Generator 900 MHz Low Voltage LVDS Clock Synthesizer Low–Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver Low Skew CMOS PLL 68060 Clock Driver INSERT PRODUCT NAME AND DOCUMENT TITLE Innovate with IDT and accelerate your future networks. Contact: www ...