mpc92432 Freescale Semiconductor, Inc, mpc92432 Datasheet - Page 4

• Manufacturer Part Number: mpc92432
• Description: 1360 Mhz Low Voltage Clock Synthesizer
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
Table 2. Function Table
1.
2.
MPC92432
Inputs
REF_SEL
M[9:0]
NA[2:0]
NB
P
PLOAD
ADR[1:0]
SDA, SCL
BYPASS
TEST_EN
CLK_STOPx
MR
Outputs
LOCK
Control
Default states are set by internal input pull-up or pull-down resistors of 75 k:
If f
REF
= 16 MHz, the default configuration will result in a output frequency of 250 MHz
01 1111 0100b
Default
010
00
1
0
1
0
1
0
1
1
2
Selects REF_CLK input as PLL reference clock
PLL feedback divider (10-bit) parallel programming interface
PLL post-divider parallel programming interface. See Table 9
PLL post-divider parallel programming interface. See Table 10
PLL pre-divider parallel programming interface. See Table 8
Selects the parallel programming interface. The
internal PLL divider settings (M, NA, NB and P) are
equal to the setting of the hardware pins. Leaving the
M, NA, NB and P pins open (floating) results in a
default PLL configuration with f
application/programming section.
Address bit = 0
See Programming the MPC92432
PLL function bypassed
Application mode. Test mode disabled.
Output Qx is disabled in logic low state. Synchronous
disable is only guaranteed if NB = 0.
The device is reset. The output frequency is zero and
the outputs are asynchronously forced to logic low
state.
After releasing reset (upon the rising edge of MR and
independent on the state of PLOAD), the MPC92432
reads the parallel interface (M, NA, NB and P) to
acquire a valid startup frequency configuration. See
application/programming section.
PLL is not locked
f
f
QA
QB
=f
=f
Freescale Semiconductor, Inc.
REF
REF
For More Information On This Product,
÷ N
÷ (N
A
A
and
· N
B
Go to: www.freescale.com
)
0
OUT
4
= 250 MHz. See
Selects the XTAL interface as PLL reference clock
Selects the serial (I
internal PLL divider settings (M, NA, NB and P) are set
and read through the serial interface.
Address bit = 1
PLL function enabled
Factory test mode is enabled
Output Qx is synchronously enabled
The PLL attempts to lock to the reference signal.
The t
PLL is frequency locked
f
f
QA
QB
LOCK
= (f
= (f
REF
REF
specification applies.
÷ P) · M ÷ N
÷ P) · M ÷ (N
2
C) programming interface. The
A
1
A
and
· N
TIMING SOLUTIONS
B
)